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| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-09-27 18:34:24 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2022-10-17 19:47:09 +0300 |
| commit | cb70c0d8b50a4051743fb42d2fc730f268864361 (patch) | |
| tree | cb5ee3cb50c4a565dbecd9c155ec8a42d8b88221 | |
| parent | 2f1aad93a1d4a86bb1249f7f94f4e696cde20232 (diff) | |
| download | linux-cb70c0d8b50a4051743fb42d2fc730f268864361.tar.xz | |
dt-bindings: pinctrl: qcom,sc7280-lpass-lpi: fix matching pin config
The LPASS pin controller follows generic pin-controller bindings, so
just like TLMM, should have subnodes with '-state' and '-pins'.
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220927153429.55365-8-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml index 624e14f00790..a8a48b684692 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -37,9 +37,17 @@ properties: gpio-ranges: maxItems: 1 -#PIN CONFIGURATION NODES patternProperties: - '-pins$': + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sc7280-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sc7280-lpass-state" + additionalProperties: false + +$defs: + qcom-sc7280-lpass-state: type: object description: Pinctrl node's client devices use subnodes for desired pin configuration. @@ -116,4 +124,21 @@ examples: gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 15>; + + dmic01-state { + dmic01-clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + }; + + dmic01-clk-sleep-pins { + pins = "gpio6"; + function = "dmic1_clk"; + }; + }; + + tx-swr-data-sleep-state { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + }; }; |