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authorKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-03-11 18:27:07 +0300
committerDinh Nguyen <dinguyen@kernel.org>2021-03-23 19:03:36 +0300
commitcdb1e8b4f4c2e515bfe3fd4d9d49bb9a5fc3806f (patch)
treed880ae1e261ab96bb7679b2a76238a59b6dad31c
parent4a9a1a5602d82c079325bf37466af0b67d6c0b9e (diff)
downloadlinux-cdb1e8b4f4c2e515bfe3fd4d9d49bb9a5fc3806f.tar.xz
clk: socfpga: allow compile testing of Stratix 10 / Agilex clocks
The Stratix 10 / Agilex / N5X clocks do not use anything other than OF or COMMON_CLK so they should be compile testable on most of the platforms. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/socfpga/Kconfig15
2 files changed, 13 insertions, 4 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 96802294d35a..9b582b3fca34 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -104,7 +104,7 @@ obj-y += renesas/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
obj-$(CONFIG_CLK_SIFIVE) += sifive/
-obj-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga/
+obj-y += socfpga/
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_ARCH_STI) += st/
diff --git a/drivers/clk/socfpga/Kconfig b/drivers/clk/socfpga/Kconfig
index b6c5b9737174..b62ede8cad01 100644
--- a/drivers/clk/socfpga/Kconfig
+++ b/drivers/clk/socfpga/Kconfig
@@ -1,6 +1,15 @@
# SPDX-License-Identifier: GPL-2.0
+config CLK_INTEL_SOCFPGA
+ bool "Intel SoCFPGA family clock support" if COMPILE_TEST && !ARCH_INTEL_SOCFPGA
+ default ARCH_INTEL_SOCFPGA
+ help
+ Support for the clock controllers present on Intel SoCFPGA and eASIC
+ devices like Stratix 10, Agilex and N5X eASIC.
+
+if CLK_INTEL_SOCFPGA
+
config CLK_INTEL_SOCFPGA64
- bool
- # Intel Stratix / Agilex / N5X clock controller support
+ bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
default ARM64 && ARCH_INTEL_SOCFPGA
- depends on ARM64 && ARCH_INTEL_SOCFPGA
+
+endif # CLK_INTEL_SOCFPGA