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authorLukas Wunner <lukas@wunner.de>2023-12-17 13:13:32 +0300
committerRob Herring <robh@kernel.org>2024-01-09 19:56:18 +0300
commitd3b8b0855a1181b5a9f8ef58022474f34cba09fd (patch)
tree327454159a07dbb2dfec3436ffadbff626374c30
parent26c9d152ebf3a16661f2d2a619bd71099c71299d (diff)
downloadlinux-d3b8b0855a1181b5a9f8ef58022474f34cba09fd.tar.xz
dt-bindings: tpm: Convert Google Cr50 bindings to DT schema
Convert the devicetree bindings for the Google Security Chip H1 running Cr50 firmware to DT schema. The chip can be attached to SPI or I²C. Existing devicetrees use the same "google,cr50" compatible string for both cases without additionally specifying a generic "tcg,tpm_tis-spi" or "tcg,tpm-tis-i2c" compatible. The chip therefore cannot be documented in the tcg,tpm_tis-spi.yaml and tcg,tpm-tis-i2c.yaml schemas: The validator would select both of them and complain about SPI properties when the chip is an I²C peripheral. So document the chip in a schema of its own which includes both, SPI and I²C properties by reference. Signed-off-by: Lukas Wunner <lukas@wunner.de> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/52635205818ab201cacb0c0f37c7fa48149c7f8e.1702806810.git.lukas@wunner.de Signed-off-by: Rob Herring <robh@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/security/tpm/google,cr50.txt19
-rw-r--r--Documentation/devicetree/bindings/tpm/google,cr50.yaml65
2 files changed, 65 insertions, 19 deletions
diff --git a/Documentation/devicetree/bindings/security/tpm/google,cr50.txt b/Documentation/devicetree/bindings/security/tpm/google,cr50.txt
deleted file mode 100644
index cd69c2efdd37..000000000000
--- a/Documentation/devicetree/bindings/security/tpm/google,cr50.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus.
-
-H1 Secure Microcontroller running Cr50 firmware provides several
-functions, including TPM-like functionality. It communicates over
-SPI using the FIFO protocol described in the PTP Spec, section 6.
-
-Required properties:
-- compatible: Should be "google,cr50".
-- spi-max-frequency: Maximum SPI frequency.
-
-Example:
-
-&spi0 {
- tpm@0 {
- compatible = "google,cr50";
- reg = <0>;
- spi-max-frequency = <800000>;
- };
-};
diff --git a/Documentation/devicetree/bindings/tpm/google,cr50.yaml b/Documentation/devicetree/bindings/tpm/google,cr50.yaml
new file mode 100644
index 000000000000..9302e12e9fc7
--- /dev/null
+++ b/Documentation/devicetree/bindings/tpm/google,cr50.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/tpm/google,cr50.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Google Security Chip H1 (running Cr50 firmware)
+
+maintainers:
+ - Andrey Pronin <apronin@chromium.org>
+
+description: |
+ Google has designed a family of security chips called "Titan".
+ One member is the H1 built into Chromebooks and running Cr50 firmware:
+ https://www.osfc.io/2018/talks/google-secure-microcontroller-and-ccd-closed-case-debugging/
+
+ The chip provides several functions, including TPM 2.0 like functionality.
+ It communicates over SPI or I²C using the FIFO protocol described in the
+ TCG PC Client Platform TPM Profile Specification for TPM 2.0 (PTP), sec 6:
+ https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
+
+properties:
+ compatible:
+ const: google,cr50
+
+allOf:
+ - $ref: tpm-common.yaml#
+
+anyOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+ - $ref: tcg,tpm-tis-i2c.yaml#/properties/reg
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm@0 {
+ reg = <0>;
+ compatible = "google,cr50";
+ spi-max-frequency = <800000>;
+ };
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tpm@50 {
+ compatible = "google,cr50";
+ reg = <0x50>;
+ interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cr50_int>;
+ };
+ };