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| author | Paul Barker <paul.barker.ct@bp.renesas.com> | 2024-03-20 11:28:31 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-03-26 11:30:44 +0300 |
| commit | e56321e48db4c57c9f389592ef6bbfb24affd0fd (patch) | |
| tree | 873aee82bcf10ff9446b38406491ed4c82d08c45 | |
| parent | b8ae9d344d09b73361493054fbde15b9f5ebe91a (diff) | |
| download | linux-e56321e48db4c57c9f389592ef6bbfb24affd0fd.tar.xz | |
clk: renesas: r9a07g044: Mark resets array as const
The r9a07g044_resets array describes the reset signals in this SoC and
does not change at runtime.
Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240320082831.9666-2-paul.barker.ct@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/r9a07g044-cpg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 48404cafea3f..f6df3f7a31b5 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -368,7 +368,7 @@ static const struct { #endif }; -static struct rzg2l_reset r9a07g044_resets[] = { +static const struct rzg2l_reset r9a07g044_resets[] = { DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0), DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1), DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0), |