diff options
| author | Boris Brezillon <boris.brezillon@collabora.com> | 2020-05-11 09:49:15 +0300 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2020-05-11 10:51:43 +0300 |
| commit | ec7cfc3d763c761ff1ad5a4e66c4f94098d7e161 (patch) | |
| tree | c559f53d8f70301f64b198d22294f2937733faf6 | |
| parent | 22dc5f9d490655a4ae1fbc55f93daa8e85b1c38f (diff) | |
| download | linux-ec7cfc3d763c761ff1ad5a4e66c4f94098d7e161.tar.xz | |
mtd: rawnand: Add a NAND_NO_BBM_QUIRK flag
Some controllers with embedded ECC engines override the BBM marker with
data or ECC bytes, thus making bad block detection through bad block
marker impossible. Let's flag those chips so the core knows it shouldn't
check the BBM and consider all blocks good.
This should allow us to get rid of two implementers of the
legacy.block_bad() hook.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20200511064917.6255-1-boris.brezillon@collabora.com
| -rw-r--r-- | drivers/mtd/nand/raw/nand_base.c | 3 | ||||
| -rw-r--r-- | include/linux/mtd/rawnand.h | 8 |
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index ba37ca9c1260..2d2a216af120 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -395,6 +395,9 @@ static int nand_block_bad(struct nand_chip *chip, loff_t ofs) static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs) { + if (chip->options & NAND_NO_BBM_QUIRK) + return 0; + if (chip->legacy.block_bad) return chip->legacy.block_bad(chip, ofs); diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 406e9ff0f45c..0f45b6984ad1 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -221,6 +221,14 @@ enum nand_ecc_algo { #define NAND_BBM_SECONDPAGE BIT(25) #define NAND_BBM_LASTPAGE BIT(26) +/* + * Some controllers with pipelined ECC engines override the BBM marker with + * data or ECC bytes, thus making bad block detection through bad block marker + * impossible. Let's flag those chips so the core knows it shouldn't check the + * BBM and consider all blocks good. + */ +#define NAND_NO_BBM_QUIRK BIT(27) + /* Cell info constants */ #define NAND_CI_CHIPNR_MSK 0x03 #define NAND_CI_CELLTYPE_MSK 0x0C |