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authorNicholas Piggin <npiggin@gmail.com>2019-06-28 08:33:32 +0300
committerMichael Ellerman <mpe@ellerman.id.au>2019-07-02 14:39:49 +0300
commitf30a5e68f026f3214a9392391537adaa79996b24 (patch)
treeaae2e59629903f03e463e905cf59b3c2eb510288
parentd7fb34c704719d3c91455297678aa75d9da95817 (diff)
downloadlinux-f30a5e68f026f3214a9392391537adaa79996b24.tar.xz
powerpc/tm: update comment about interrupt re-entrancy
Since the system reset interrupt began to use its own stack, and machine check interrupts have done so for some time, r1 can be changed without clearing MSR[RI], provided no other interrupts (including SLB misses) are taken. MSR[RI] does have to be cleared when using SCRATCH0, however. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
-rw-r--r--arch/powerpc/kernel/tm.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index 9fabdce255cd..6ba0fdd1e7f8 100644
--- a/arch/powerpc/kernel/tm.S
+++ b/arch/powerpc/kernel/tm.S
@@ -148,7 +148,7 @@ _GLOBAL(tm_reclaim)
/* Stash the stack pointer away for use after reclaim */
std r1, PACAR1(r13)
- /* Clear MSR RI since we are about to change r1, EE is already off. */
+ /* Clear MSR RI since we are about to use SCRATCH0, EE is already off */
li r5, 0
mtmsrd r5, 1
@@ -474,7 +474,7 @@ restore_gprs:
REST_GPR(7, r7)
- /* Clear MSR RI since we are about to change r1. EE is already off */
+ /* Clear MSR RI since we are about to use SCRATCH0. EE is already off */
li r5, 0
mtmsrd r5, 1