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| author | Bjorn Helgaas <bhelgaas@google.com> | 2023-08-15 00:28:22 +0300 |
|---|---|---|
| committer | Jonathan Corbet <corbet@lwn.net> | 2023-08-18 20:29:03 +0300 |
| commit | d56b699d76d1b352f7a3d3a0a3e91c79b8612d94 (patch) | |
| tree | 2a368f3e2e17f7a516bf39e055f79d8c79a74885 /Documentation/arch/xtensa/atomctl.rst | |
| parent | ebab9426cd73c45945b44344ca904b343f0ca070 (diff) | |
| download | linux-d56b699d76d1b352f7a3d3a0a3e91c79b8612d94.tar.xz | |
Documentation: Fix typos
Fix typos in Documentation.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20230814212822.193684-4-helgaas@kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/arch/xtensa/atomctl.rst')
| -rw-r--r-- | Documentation/arch/xtensa/atomctl.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/arch/xtensa/atomctl.rst b/Documentation/arch/xtensa/atomctl.rst index 1ecbd0ba9a2e..75d174169430 100644 --- a/Documentation/arch/xtensa/atomctl.rst +++ b/Documentation/arch/xtensa/atomctl.rst @@ -23,7 +23,7 @@ doing a Cached (WB) transaction and use the Memory RCW for un-cached operations. For systems without an coherent cache controller, non-MX, we always -use the memory controllers RCW, thought non-MX controlers likely +use the memory controllers RCW, though non-MX controllers likely support the Internal Operation. CUSTOMER-WARNING: |