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authorMarc Zyngier <marc.zyngier@arm.com>2013-11-28 22:24:58 +0400
committerChristoffer Dall <christoffer.dall@linaro.org>2014-07-11 15:57:30 +0400
commit63f8344cb4917e5219d07cfd6fcd50860bcf5360 (patch)
tree5815d777e0d62ca21548caef7ff9452ab5c98103 /Documentation/arm64
parent96f68023bfb359a508e7e106eae5e3904669a999 (diff)
downloadlinux-63f8344cb4917e5219d07cfd6fcd50860bcf5360.tar.xz
arm64: boot protocol documentation update for GICv3
Linux has some requirements that must be satisfied in order to boot on a system built with a GICv3. Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/booting.txt8
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.txt b/Documentation/arm64/booting.txt
index 37fc4f632176..da1d4bf32ac2 100644
--- a/Documentation/arm64/booting.txt
+++ b/Documentation/arm64/booting.txt
@@ -141,6 +141,14 @@ Before jumping into the kernel, the following conditions must be met:
the kernel image will be entered must be initialised by software at a
higher exception level to prevent execution in an UNKNOWN state.
+ For systems with a GICv3 interrupt controller:
+ - If EL3 is present:
+ ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
+ ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
+ - If the kernel is entered at EL1:
+ ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
+ ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
+
The requirements described above for CPU mode, caches, MMUs, architected
timers, coherency and system registers apply to all CPUs. All CPUs must
enter the kernel in the same exception level.