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authorVineet Gupta <vgupta@synopsys.com>2015-03-06 11:38:20 +0300
committerVineet Gupta <vgupta@synopsys.com>2015-06-22 11:36:55 +0300
commit820970a5aa3c98be26e1df64da4b93294d20d4e7 (patch)
treea9b134845a29a0b789226a7ff1202eef7f99a4ac /Documentation/devicetree/bindings/arc
parent10d11e580c50f8a6718a58f92198dbc031e63b0a (diff)
downloadlinux-820970a5aa3c98be26e1df64da4b93294d20d4e7.tar.xz
ARCv2: [intc] HS38 core interrupt controller
Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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diff --git a/Documentation/devicetree/bindings/arc/archs-intc.txt b/Documentation/devicetree/bindings/arc/archs-intc.txt
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+* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
+
+Properties:
+
+- compatible: "snps,archs-intc"
+- interrupt-controller: This is an interrupt controller.
+- #interrupt-cells: Must be <1>.
+
+ Single Cell "interrupts" property of a device specifies the IRQ number
+ between 16 to 256
+
+ intc accessed via the special ARC AUX register interface, hence "reg" property
+ is not specified.
+
+Example:
+
+ intc: interrupt-controller {
+ compatible = "snps,archs-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <16 17 18 19 20 21 22 23 24 25>;
+ };