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author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-02-06 12:26:22 +0300 |
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committer | Rob Herring <robh@kernel.org> | 2023-02-08 00:47:27 +0300 |
commit | 33887fce47e17cdd4df44f3d98320a27908897fa (patch) | |
tree | 18ad054e0b80264b79e83a70227b5ff114dc2a8d /Documentation/devicetree/bindings/bus | |
parent | f9b8556d5799b612404e19b21dd7624d551f71df (diff) | |
download | linux-33887fce47e17cdd4df44f3d98320a27908897fa.tar.xz |
dt-bindings: intel,ixp4xx-expansion-bus: split out peripheral properties
The properties of devices in IXP4xx expansion bus need to be also
applied to actual devices' bindings. Prepare for this by splitting them
to separate intel,ixp4xx-expansion-peripheral-props binding, just like
other memory-controller peripheral properties.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/20230206092624.22922-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/bus')
-rw-r--r-- | Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml | 168 |
1 files changed, 0 insertions, 168 deletions
diff --git a/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml b/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml deleted file mode 100644 index 5fb4e7bfa4da..000000000000 --- a/Documentation/devicetree/bindings/bus/intel,ixp4xx-expansion-bus-controller.yaml +++ /dev/null @@ -1,168 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/bus/intel,ixp4xx-expansion-bus-controller.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Intel IXP4xx Expansion Bus Controller - -description: | - The IXP4xx expansion bus controller handles access to devices on the - memory-mapped expansion bus on the Intel IXP4xx family of system on chips, - including IXP42x, IXP43x, IXP45x and IXP46x. - -maintainers: - - Linus Walleij <linus.walleij@linaro.org> - -properties: - $nodename: - pattern: '^bus@[0-9a-f]+$' - - compatible: - items: - - enum: - - intel,ixp42x-expansion-bus-controller - - intel,ixp43x-expansion-bus-controller - - intel,ixp45x-expansion-bus-controller - - intel,ixp46x-expansion-bus-controller - - const: syscon - - reg: - description: Control registers for the expansion bus, these are not - inside the memory range handled by the expansion bus. - maxItems: 1 - - native-endian: - $ref: /schemas/types.yaml#/definitions/flag - description: The IXP4xx has a peculiar MMIO access scheme, as it changes - the access pattern for words (swizzling) on the bus depending on whether - the SoC is running in big-endian or little-endian mode. Thus the - registers must always be accessed using native endianness. - - "#address-cells": - description: | - The first cell is the chip select number. - The second cell is the address offset within the bank. - const: 2 - - "#size-cells": - const: 1 - - ranges: true - dma-ranges: true - -patternProperties: - "^.*@[0-7],[0-9a-f]+$": - description: Devices attached to chip selects are represented as - subnodes. - type: object - - properties: - intel,ixp4xx-eb-t1: - description: Address timing, extend address phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 3 - - intel,ixp4xx-eb-t2: - description: Setup chip select timing, extend setup phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 3 - - intel,ixp4xx-eb-t3: - description: Strobe timing, extend strobe phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 15 - - intel,ixp4xx-eb-t4: - description: Hold timing, extend hold phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 3 - - intel,ixp4xx-eb-t5: - description: Recovery timing, extend recovery phase with n cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - maximum: 15 - - intel,ixp4xx-eb-cycle-type: - description: The type of cycles to use on the expansion bus for this - chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2] - - intel,ixp4xx-eb-byte-access-on-halfword: - description: Allow byte read access on half word devices. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-hpi-hrdy-pol-high: - description: Set HPI HRDY polarity to active high when using HPI. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-mux-address-and-data: - description: Multiplex address and data on the data bus. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-ahb-split-transfers: - description: Enable AHB split transfers. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-write-enable: - description: Enable write cycles. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - - intel,ixp4xx-eb-byte-access: - description: Expansion bus uses only 8 bits. The default is to use - 16 bits. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - -required: - - compatible - - reg - - native-endian - - "#address-cells" - - "#size-cells" - - ranges - - dma-ranges - -additionalProperties: false - -examples: - - | - #include <dt-bindings/interrupt-controller/irq.h> - bus@50000000 { - compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; - reg = <0xc4000000 0x28>; - native-endian; - #address-cells = <2>; - #size-cells = <1>; - ranges = <0 0x0 0x50000000 0x01000000>, - <1 0x0 0x51000000 0x01000000>; - dma-ranges = <0 0x0 0x50000000 0x01000000>, - <1 0x0 0x51000000 0x01000000>; - flash@0,0 { - compatible = "intel,ixp4xx-flash", "cfi-flash"; - bank-width = <2>; - reg = <0 0x00000000 0x1000000>; - intel,ixp4xx-eb-t3 = <3>; - intel,ixp4xx-eb-cycle-type = <0>; - intel,ixp4xx-eb-byte-access-on-halfword = <1>; - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <0>; - }; - serial@1,0 { - compatible = "exar,xr16l2551", "ns8250"; - reg = <1 0x00000000 0x10>; - interrupt-parent = <&gpio0>; - interrupts = <4 IRQ_TYPE_LEVEL_LOW>; - clock-frequency = <1843200>; - intel,ixp4xx-eb-t3 = <3>; - intel,ixp4xx-eb-cycle-type = <1>; - intel,ixp4xx-eb-write-enable = <1>; - intel,ixp4xx-eb-byte-access = <1>; - }; - }; |