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| author | Komal Bajaj <quic_kbajaj@quicinc.com> | 2023-08-30 13:56:49 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-09-20 05:57:53 +0300 |
| commit | 8e2506d0123149a7b7846fbabbf4295b6005faf4 (patch) | |
| tree | 5242a0957be415b2986bc3f78928c7f5214c55ef /Documentation/devicetree/bindings/cache | |
| parent | 5692aeea5bcb9331e956628c3bc8fc9afcc9765d (diff) | |
| download | linux-8e2506d0123149a7b7846fbabbf4295b6005faf4.tar.xz | |
dt-bindings: cache: qcom,llcc: Add LLCC compatible for QDU1000/QRU1000
Add LLCC compatible for QDU1000/QRU1000 SoCs and add optional
nvmem-cells and nvmem-cell-names properties to support multiple
configurations for multi channel DDR.
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230830105654.28057-2-quic_kbajaj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/cache')
| -rw-r--r-- | Documentation/devicetree/bindings/cache/qcom,llcc.yaml | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 44892aa589fd..580f9a97ddf7 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: enum: + - qcom,qdu1000-llcc - qcom,sc7180-llcc - qcom,sc7280-llcc - qcom,sc8180x-llcc @@ -44,6 +45,14 @@ properties: interrupts: maxItems: 1 + nvmem-cells: + items: + - description: Reference to an nvmem node for multi channel DDR + + nvmem-cell-names: + items: + - const: multi-chan-ddr + required: - compatible - reg @@ -92,6 +101,7 @@ allOf: compatible: contains: enum: + - qcom,qdu1000-llcc - qcom,sc8180x-llcc - qcom,sc8280xp-llcc then: |