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| author | Stephen Boyd <sboyd@kernel.org> | 2023-08-31 00:39:58 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-08-31 00:39:58 +0300 |
| commit | 41680df0975e04b959a28bf6ab85fd6a307ae0ea (patch) | |
| tree | 36baf601d2281987d5dcaa8d04ccf3e11f548247 /Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | |
| parent | 3462100cf38b192e7ef1b3a11c4f6d64c5e8066d (diff) | |
| parent | 75d1d3a433f0a0748a89eb074830e9b635a19fd2 (diff) | |
| download | linux-41680df0975e04b959a28bf6ab85fd6a307ae0ea.tar.xz | |
Merge branch 'clk-qcom' into clk-next
* clk-qcom: (87 commits)
clk: qcom: Fix SM_GPUCC_8450 dependencies
clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC
clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags
clk: qcom: gcc-ipq5018: change some variable static
clk: qcom: gcc-ipq4019: add missing networking resets
dt-bindings: clock: qcom: ipq4019: add missing networking resets
clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC
dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC
clk: qcom: gcc-qdu1000: Update the RCGs ops
clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops
clk: qcom: gcc-qdu1000: Add support for GDSCs
clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support
clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock
clk: qcom: gcc-qdu1000: Fix clkref clocks handling
clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling
dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs
clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs
clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock
clk: qcom: ipq5332: drop the mem noc clocks
clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks
...
Diffstat (limited to 'Documentation/devicetree/bindings/clock/qcom,gpucc.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,gpucc.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index a00216b3b15a..f369fa34e00c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Graphics Clock & Reset Controller maintainers: - - Taniya Das <tdas@codeaurora.org> + - Taniya Das <quic_tdas@quicinc.com> description: | Qualcomm graphics clock control module provides the clocks, resets and power |