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| author | Peng Fan <peng.fan@nxp.com> | 2024-04-01 16:28:17 +0300 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@linaro.org> | 2024-04-22 12:58:10 +0300 |
| commit | c6e87b066756ec4b3f5f9061b508f3bd724ec652 (patch) | |
| tree | 00088e503118f441ad1f43346a632cf770c6311e /Documentation/devicetree/bindings/clock | |
| parent | b773f5ad2bfd2d00bd2c5ea7022bc5b86d23a1b7 (diff) | |
| download | linux-c6e87b066756ec4b3f5f9061b508f3bd724ec652.tar.xz | |
dt-bindings: clock: support i.MX95 Display Master CSR module
i.MX95 DISPLAY_MASTER_CSR includes registers to control DSI clock settings,
clock gating, and pixel link select. Add dt-schema for it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20240401-imx95-blk-ctl-v6-3-84d4eca1e759@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml new file mode 100644 index 000000000000..07f7412e7658 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX95 Display Master Block Control + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +properties: + compatible: + items: + - const: nxp,imx95-display-master-csr + - const: syscon + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See + include/dt-bindings/clock/nxp,imx95-clock.h + + mux-controller: + type: object + $ref: /schemas/mux/reg-mux.yaml + +required: + - compatible + - reg + - '#clock-cells' + - mux-controller + - power-domains + - clocks + +additionalProperties: false + +examples: + - | + syscon@4c410000 { + compatible = "nxp,imx95-display-master-csr", "syscon"; + reg = <0x4c410000 0x10000>; + #clock-cells = <1>; + clocks = <&scmi_clk 62>; + power-domains = <&scmi_devpd 3>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */ + idle-states = <0>; + }; + }; +... |