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authorMichal Simek <michal.simek@amd.com>2024-01-31 12:17:28 +0300
committerMichal Simek <michal.simek@amd.com>2024-02-06 10:01:32 +0300
commitd8764d347bd737efec00fae81133ffad0ae084bb (patch)
treecf46c333d504daa1f4c72302fc074d9fb463f0a5 /Documentation/devicetree/bindings/firmware
parentdbcd27526e6abee1c65cdf350c232a6e5c2afb47 (diff)
downloadlinux-d8764d347bd737efec00fae81133ffad0ae084bb.tar.xz
dt-bindings: firmware: xilinx: Describe soc-nvmem subnode
Describe soc-nvmem subnode as the part of firmware node. The name can't be pure nvmem because dt-schema already defines it as array property that's why different name should be used. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/24fe6adbf2424360618e8f5ca541ebfd8bb0723e.1706692641.git.michal.simek@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'Documentation/devicetree/bindings/firmware')
-rw-r--r--Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml18
1 files changed, 18 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
index 7586fbff7ad6..ab8f32c440df 100644
--- a/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
+++ b/Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
@@ -62,6 +62,12 @@ properties:
interface.
type: object
+ soc-nvmem:
+ $ref: /schemas/nvmem/xlnx,zynqmp-nvmem.yaml#
+ description: The ZynqMP MPSoC provides access to the hardware related data
+ like SOC revision, IDCODE and specific purpose efuses.
+ type: object
+
pcap:
$ref: /schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml
description: The ZynqMP SoC uses the PCAP (Processor Configuration Port) to
@@ -110,6 +116,18 @@ examples:
firmware {
zynqmp_firmware: zynqmp-firmware {
#power-domain-cells = <1>;
+ soc-nvmem {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc_revision: soc-revision@0 {
+ reg = <0x0 0x4>;
+ };
+ };
+ };
gpio {
compatible = "xlnx,zynqmp-gpio-modepin";
gpio-controller;