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author | Yoshihiro Kaneko <ykaneko0929@gmail.com> | 2020-05-07 10:55:03 +0300 |
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committer | Rob Herring <robh@kernel.org> | 2020-05-15 05:48:36 +0300 |
commit | 0be4ae74881c96ae8ff718bcfb517415ab61a41e (patch) | |
tree | 6adc16c47a19da610e446438ba1033ef5b98391e /Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml | |
parent | fba5618451d2b3af5e55f8af5ce9c5d3677ad9c4 (diff) | |
download | linux-0be4ae74881c96ae8ff718bcfb517415ab61a41e.tar.xz |
dt-bindings: irqchip: renesas-intc-irqpin: Convert to json-schema
Convert the Renesas Interrupt Controller (INTC) for external pins Device
Tree binding documentation to json-schema.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Co-developed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[robh: drop allOf]
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml | 107 |
1 files changed, 107 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml new file mode 100644 index 000000000000..f4aae56c6469 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Interrupt Controller (INTC) for external pins + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +properties: + compatible: + items: + - enum: + - renesas,intc-irqpin-r8a7740 # R-Mobile A1 + - renesas,intc-irqpin-r8a7778 # R-Car M1A + - renesas,intc-irqpin-r8a7779 # R-Car H1 + - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5 + - const: renesas,intc-irqpin + + reg: + minItems: 5 + items: + - description: Interrupt control register + - description: Interrupt priority register + - description: Interrupt source register + - description: Interrupt mask register + - description: Interrupt mask clear register + - description: Interrupt control register for ICR0 with IRLM0 bit + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + minItems: 1 + maxItems: 8 + + sense-bitfield-width: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4] + default: 4 + description: + Width of a single sense bitfield in the SENSE register, if different from the + default. + + control-parent: + type: boolean + description: + Disable and enable interrupts on the parent interrupt controller, needed for some + broken implementations. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + +if: + properties: + compatible: + contains: + enum: + - renesas,intc-irqpin-r8a7740 + - renesas,intc-irqpin-sh73a0 +then: + required: + - clocks + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7740-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + irqpin1: interrupt-controller@e6900004 { + compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; + reg = <0xe6900004 4>, + <0xe6900014 4>, + <0xe6900024 1>, + <0xe6900044 1>, + <0xe6900064 1>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; + power-domains = <&pd_a4s>; + }; |