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| author | Vasant Hegde <vasant.hegde@amd.com> | 2023-03-10 12:00:00 +0300 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2023-03-28 16:31:31 +0300 |
| commit | f594496403fa383259aa7dfad92f383a2ee07e1b (patch) | |
| tree | 2a533c413696fe7b68691b6517f172d2a528e224 /Documentation/devicetree/bindings/iommu | |
| parent | 4d4a0dbab2b998692f54fa6f7a9d2eb675110743 (diff) | |
| download | linux-f594496403fa383259aa7dfad92f383a2ee07e1b.tar.xz | |
iommu/amd: Add 5 level guest page table support
Newer AMD IOMMU supports 5 level guest page table (v2 page table). If both
processor and IOMMU supports 5 level page table then enable it. Otherwise
fall back to 4 level page table.
Co-developed-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Reviewed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Link: https://lore.kernel.org/r/20230310090000.1117786-1-vasant.hegde@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'Documentation/devicetree/bindings/iommu')
0 files changed, 0 insertions, 0 deletions