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authorCaesar Wang <wxt@rock-chips.com>2015-10-27 10:31:44 +0300
committerJassi Brar <jaswinder.singh@linaro.org>2016-03-11 06:37:17 +0300
commita7065bc37b6764df681d12b1059415a0a262c4e0 (patch)
tree1694a4caff63eb39faaa6e6cc989b949392f5d61 /Documentation/devicetree/bindings/mailbox
parent14d653af4e32b1ae2964e5b2847ef6be191fee64 (diff)
downloadlinux-a7065bc37b6764df681d12b1059415a0a262c4e0.tar.xz
dt-bindings: rockchip-mailbox: Add mailbox controller document on Rockchip SoCs
This add the necessary binding documentation for mailbox found on RK3368 SoC. Signed-off-by: Caesar Wang <wxt@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mailbox')
-rw-r--r--Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt32
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diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
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+++ b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt
@@ -0,0 +1,32 @@
+Rockchip mailbox
+
+The Rockchip mailbox is used by the Rockchip CPU cores to communicate
+requests to MCU processor.
+
+Refer to ./mailbox.txt for generic information about mailbox device-tree
+bindings.
+
+Required properties:
+
+ - compatible: should be one of the following.
+ - "rockchip,rk3368-mbox" for rk3368
+ - reg: physical base address of the controller and length of memory mapped
+ region.
+ - interrupts: The interrupt number to the cpu. The interrupt specifier format
+ depends on the interrupt controller.
+ - #mbox-cells: Common mailbox binding property to identify the number
+ of cells required for the mailbox specifier. Should be 1
+
+Example:
+--------
+
+/* RK3368 */
+mbox: mbox@ff6b0000 {
+ compatible = "rockchip,rk3368-mailbox";
+ reg = <0x0 0xff6b0000 0x0 0x1000>,
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+};