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author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-06-05 05:56:20 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-06-05 05:56:20 +0300 |
commit | 828f3e18e1cb98c68fc6db4d5113513d4a267775 (patch) | |
tree | e1d813f2122dee697e896166917d58f46dff82c5 /Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml | |
parent | 298743c193bb50b5d65b9285eb7206ffb31d412d (diff) | |
parent | b5f73d47f34b238221ac771b5fe4907df621d7cb (diff) | |
download | linux-828f3e18e1cb98c68fc6db4d5113513d4a267775.tar.xz |
Merge tag 'arm-drivers-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM/SoC driver updates from Arnd Bergmann:
"These are updates to SoC specific drivers that did not have another
subsystem maintainer tree to go through for some reason:
- Some bus and memory drivers for the MIPS P5600 based Baikal-T1 SoC
that is getting added through the MIPS tree.
- There are new soc_device identification drivers for TI K3, Qualcomm
MSM8939
- New reset controller drivers for NXP i.MX8MP, Renesas RZ/G1H, and
Hisilicon hi6220
- The SCMI firmware interface can now work across ARM SMC/HVC as a
transport.
- Mediatek platforms now use a new driver for their "MMSYS" hardware
block that controls clocks and some other aspects in behalf of the
media and gpu drivers.
- Some Tegra processors have improved power management support,
including getting woken up by the PMIC and cluster power down
during idle.
- A new v4l staging driver for Tegra is added.
- Cleanups and minor bugfixes for TI, NXP, Hisilicon, Mediatek, and
Tegra"
* tag 'arm-drivers-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (155 commits)
clk: sprd: fix compile-testing
bus: bt1-axi: Build the driver into the kernel
bus: bt1-apb: Build the driver into the kernel
bus: bt1-axi: Use sysfs_streq instead of strncmp
bus: bt1-axi: Optimize the return points in the driver
bus: bt1-apb: Use sysfs_streq instead of strncmp
bus: bt1-apb: Use PTR_ERR_OR_ZERO to return from request-regs method
bus: bt1-apb: Fix show/store callback identations
bus: bt1-apb: Include linux/io.h
dt-bindings: memory: Add Baikal-T1 L2-cache Control Block binding
memory: Add Baikal-T1 L2-cache Control Block driver
bus: Add Baikal-T1 APB-bus driver
bus: Add Baikal-T1 AXI-bus driver
dt-bindings: bus: Add Baikal-T1 APB-bus binding
dt-bindings: bus: Add Baikal-T1 AXI-bus binding
staging: tegra-video: fix V4L2 dependency
tee: fix crypto select
drivers: soc: ti: knav_qmss_queue: Make knav_gp_range_ops static
soc: ti: add k3 platforms chipid module driver
dt-bindings: soc: ti: add binding for k3 platforms chipid module
...
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml new file mode 100644 index 000000000000..1fca282f64a2 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 L2-cache Control Block + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: | + By means of the System Controller Baikal-T1 SoC exposes a few settings to + tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible + to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 + L2-cache controller block is responsible for the tuning. Its DT node is + supposed to be a child of the system controller. + +properties: + compatible: + const: baikal,bt1-l2-ctl + + reg: + maxItems: 1 + + baikal,l2-ws-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Way-select RAM accesses + default: 0 + minimum: 0 + maximum: 3 + + baikal,l2-tag-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Tag RAM accesses + default: 0 + minimum: 0 + maximum: 3 + + baikal,l2-data-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Data RAM accesses + default: 1 + minimum: 0 + maximum: 3 + +additionalProperties: false + +required: + - compatible + +examples: + - | + l2@1f04d028 { + compatible = "baikal,bt1-l2-ctl"; + reg = <0x1f04d028 0x004>; + + baikal,l2-ws-latency = <1>; + baikal,l2-tag-latency = <1>; + baikal,l2-data-latency = <2>; + }; +... |