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author | Marvin Lin <milkfafa@gmail.com> | 2023-01-11 12:32:44 +0300 |
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committer | Borislav Petkov (AMD) <bp@alien8.de> | 2023-06-12 16:13:31 +0300 |
commit | a053b7e579bdc2d0d66ee263a76214f6f1f89549 (patch) | |
tree | 8b9120d5d2a29e1dbb17e2999a06c45d28e7104b /Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml | |
parent | ac9a78681b921877518763ba0e89202254349d1b (diff) | |
download | linux-a053b7e579bdc2d0d66ee263a76214f6f1f89549.tar.xz |
dt-bindings: memory-controllers: nuvoton: Add NPCM memory controller
Add dt-bindings document for Nuvoton NPCM memory controller.
Signed-off-by: Marvin Lin <milkfafa@gmail.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230111093245.318745-3-milkfafa@gmail.com
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml b/Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml new file mode 100644 index 000000000000..ac1a5a17749d --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Memory Controller + +maintainers: + - Marvin Lin <kflin@nuvoton.com> + - Stanley Chu <yschu@nuvoton.com> + +description: | + The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction + check). + + The memory controller supports single bit error correction, double bit error + detection (in-line ECC in which a section (1/8th) of the memory device used to + store data is used for ECC storage). + + Note, the bootloader must configure ECC mode for the memory controller. + +properties: + compatible: + enum: + - nuvoton,npcm750-memory-controller + - nuvoton,npcm845-memory-controller + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm750-memory-controller"; + reg = <0xf0824000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + }; |