Merge tag 'devicetree-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull devicetree updates from Rob Herring:
 "DT core:

   - Add support for generating DT nodes for PCI devices. This is the
     groundwork for applying overlays to PCI devices containing
     non-discoverable downstream devices.

   - DT unittest additions to check reverted changesets, to test for
     refcount issues, and to test unresolved symbols. Also, various
     clean-ups of the unittest along the way.

   - Refactor node and property manipulation functions to better share
     code with old API and changeset API

   - Refactor changeset print functions to a common implementation

   - Move some platform_device specific functions into of_platform.c

  Bindings:

   - Treewide fixing of typos

   - Treewide clean-up of SPDX tags to use 'OR' consistently

   - Last chunk of dropping unnecessary quotes. With that, the check for
     unnecessary quotes is enabled in yamllint.

   - Convert ftgmac100, zynqmp-genpd, pps-gpio, syna,rmi4, and qcom,ssbi
     bindings to DT schema format

   - Add Allwinner V3s xHCI USB, Saef SF-TC154B display, QCom SM8450
     Inline Crypto Engine, QCom SM6115 UFS, QCom SDM670 PDC interrupt
     controller, Arm 2022 Cortex cores, and QCom IPQ9574 Crypto bindings

   - Fixes for Rockchip DWC PCI binding

   - Ensure all properties are evaluated on USB connector schema

   - Fix dt-check-compatible script to find of_device_id instances with
     compiler annotations"

* tag 'devicetree-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (64 commits)
  dt-bindings: usb: Add V3s compatible string for OHCI
  dt-bindings: usb: Add V3s compatible string for EHCI
  dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
  dt-bindings: vendor-prefixes: document Saef Technology
  dt-bindings: thermal: lmh: update maintainer address
  of: unittest: Fix of_unittest_pci_node() kconfig dependencies
  dt-bindings: crypto: ice: Document sm8450 inline crypto engine
  dt-bindings: ufs: qcom: Add ICE to sm8450 example
  dt-bindings: ufs: qcom: Add sm6115 binding
  dt-bindings: ufs: qcom: Add reg-names property for ICE
  dt-bindings: yamllint: Enable quoted string check
  dt-bindings: Drop remaining unneeded quotes
  of: unittest-data: Fix whitespace - angular brackets
  of: unittest-data: Fix whitespace - indentation
  of: unittest-data: Fix whitespace - blank lines
  of: unittest-data: Convert remaining overlay DTS files to sugar syntax
  of: overlay: unittest: Add test for unresolved symbol
  of: unittest: Add separators to of_unittest_overlay_high_level()
  of: unittest: Cleanup partially-applied overlays
  of: unittest: Merge of_unittest_apply{,_revert}_overlay_check()
  ...

3 files changed, 4 insertions, 4 deletions

diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
index aee7f6cf1300..2381660b324c 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -67,7 +67,7 @@ properties:
     minimum: 0
     maximum: 31
     description: the hardware id of this larb. It's only required when this
-      hardward id is not consecutive from its M4U point of view.
+      hardware id is not consecutive from its M4U point of view.
 
 required:
   - compatible
diff --git a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
index fb4920397d08..4e4af3cfc0fe 100644
--- a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
@@ -152,7 +152,7 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
       When the DRAM type is DDR3, this parameter defines the phy side CA line
-      (incluing command line, address line and clock line) drive strength.
+      (including command line, address line and clock line) drive strength.
     default: 40
 
   rockchip,phy_ddr3_dq_drv:
@@ -305,7 +305,7 @@ properties:
     description:
       Defines the self-refresh power down idle period in which memories are
       placed into self-refresh power down mode if bus is idle for
-      srpd_lite_idle nanoseonds. This parameter is for LPDDR4 only.
+      srpd_lite_idle nanoseconds. This parameter is for LPDDR4 only.
 
   rockchip,standby-idle-ns:
     description:
diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
index 75143db51411..b74ad9a3305c 100644
--- a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
@@ -12,7 +12,7 @@ maintainers:
 
 description:
   The Zynq DDR ECC controller has an optional ECC support in half-bus width
-  (16-bit) configuration. It is cappable of correcting single bit ECC errors
+  (16-bit) configuration. It is capable of correcting single bit ECC errors
   and detecting double bit ECC errors.
 
 properties: