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authorAlexandre Belloni <alexandre.belloni@bootlin.com>2018-03-20 16:07:57 +0300
committerJames Hogan <jhogan@kernel.org>2018-03-22 02:32:32 +0300
commit2707177e86ec9b25c0988c2cc827acbae409b376 (patch)
tree8953fcb77811ddcb7713e5f98805c41b22b70322 /Documentation/devicetree/bindings/mips
parentb3fd27e9150f7ac2a2bd3f61aa71aadb4db499b2 (diff)
downloadlinux-2707177e86ec9b25c0988c2cc827acbae409b376.tar.xz
dt-bindings: mips: Add bindings for Microsemi SoCs
Add bindings for Microsemi SoCs. Currently only Ocelot is supported. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Rob Herring <robh+dt@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Allan Nielsen <Allan.Nielsen@microsemi.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18854/ Signed-off-by: James Hogan <jhogan@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mips')
-rw-r--r--Documentation/devicetree/bindings/mips/mscc.txt43
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diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
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+* Microsemi MIPS CPUs
+
+Boards with a SoC of the Microsemi MIPS family shall have the following
+properties:
+
+Required properties:
+- compatible: "mscc,ocelot"
+
+
+* Other peripherals:
+
+o CPU chip regs:
+
+The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
+functionalities: chip ID, general purpose register for software use, reset
+controller, hardware status and configuration, efuses.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@71070000 {
+ compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+ reg = <0x71070000 0x1c>;
+ };
+
+
+o CPU system control:
+
+The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
+the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
+endianness, CPU bus control, CPU status.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+ syscon@70000000 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x70000000 0x2c>;
+ };