diff options
author | Miquel Raynal <miquel.raynal@bootlin.com> | 2023-08-18 17:39:53 +0300 |
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committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2023-08-18 17:40:02 +0300 |
commit | f7091fb725dcabc171c5fba28a6ce38beb08f205 (patch) | |
tree | c925483281414fe39144424157b60bfca6c565f0 /Documentation/devicetree/bindings/mtd | |
parent | a417ab334dccb603f6296cbf04c9f8059bc252eb (diff) | |
parent | 69d50d0461a182872b7f7892702fa3a1ba95950d (diff) | |
download | linux-f7091fb725dcabc171c5fba28a6ce38beb08f205.tar.xz |
Merge tag 'spi-nor/for-6.6' into mtd/next
SPI NOR core changes:
* fix assumption on enabling quad mode in
spi_nor_write_16bit_sr_and_check()
* avoid setting SRWD bit in SR if WP# signal not connected as it will
configure the SR permanently as read only. Add "no-wp" dt property.
* clarify the need for spi-nor compatibles in dt-bindings
SPI NOR manufacturer drivers changes:
* spansion:
- add support for S28HS02GT
- switch methods to use vreg_offset from SFDP instead of hardcoding
the register value
* microchip/sst:
- add support for sst26vf032b flash
* winbond:
- correct flags for Winbond w25q128
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'Documentation/devicetree/bindings/mtd')
-rw-r--r-- | Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 89959e5c47ba..58f0cea160ef 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -43,8 +43,10 @@ properties: - const: jedec,spi-nor - const: jedec,spi-nor description: - Must also include "jedec,spi-nor" for any SPI NOR flash that can be - identified by the JEDEC READ ID opcode (0x9F). + SPI NOR flashes compatible with the JEDEC SFDP standard or which may be + identified with the READ ID opcode (0x9F) do not deserve a specific + compatible. They should instead only be matched against the generic + "jedec,spi-nor" compatible. reg: minItems: 1 @@ -70,6 +72,21 @@ properties: be used on such systems, to denote the absence of a reliable reset mechanism. + no-wp: + type: boolean + description: + The status register write disable (SRWD) bit in status register, combined + with the WP# signal, provides hardware data protection for the device. When + the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard + strapped to LOW, the status register nonvolatile bits become read-only and + the WRITE STATUS REGISTER operation will not execute. The only way to exit + this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the + flash device is not connected or is wrongly tied to GND (that includes internal + pull-downs) then status register permanently becomes read-only as the SRWD bit + cannot be reset. This boolean flag can be used on such systems to avoid setting + the SRWD bit while writing the status register. WP# signal hard strapped to GND + can be a valid use case. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device. |