summaryrefslogtreecommitdiff
path: root/Documentation/devicetree/bindings/phy
diff options
context:
space:
mode:
authorShawn Lin <shawn.lin@rock-chips.com>2017-07-19 12:57:58 +0300
committerBjorn Helgaas <bhelgaas@google.com>2017-08-29 21:18:05 +0300
commit05b57273acb360d9fe5f8b8029890487e819871b (patch)
treee9f50fbadddb46d0405e2091ae029f1e66d39e1d /Documentation/devicetree/bindings/phy
parent7a55b57031b3e97bbdfe8d378e4c6989341de7be (diff)
downloadlinux-05b57273acb360d9fe5f8b8029890487e819871b.tar.xz
dt-bindings: phy-rockchip-pcie: Convert to per-lane PHY model
Deprecate the legacy Rockchip PCIe PHY and encourage users to use per-lane PHY mode by setting #phy-cells to 1. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r--Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt7
1 files changed, 6 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
index 0f6222a672ce..b496042f1f44 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
@@ -3,7 +3,6 @@ Rockchip PCIE PHY
Required properties:
- compatible: rockchip,rk3399-pcie-phy
- - #phy-cells: must be 0
- clocks: Must contain an entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must be "refclk"
@@ -11,6 +10,12 @@ Required properties:
See ../reset/reset.txt for details.
- reset-names: Must be "phy"
+Required properties for legacy PHY mode (deprecated):
+ - #phy-cells: must be 0
+
+Required properties for per-lane PHY mode (preferred):
+ - #phy-cells: must be 1
+
Example:
grf: syscon@ff770000 {