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authorVaradarajan Narayanan <varada@codeaurora.org>2017-07-31 09:34:12 +0300
committerKishon Vijay Abraham I <kishon@ti.com>2017-08-20 11:29:19 +0300
commit2d66eab1837542bdb347f514df1cd05ec1fc2969 (patch)
tree4c5b81953f9100c00a5f0e841a6f59830829cf70 /Documentation/devicetree/bindings/phy
parente88432e728ef3287b326031085893e5fc7878d2b (diff)
downloadlinux-2d66eab1837542bdb347f514df1cd05ec1fc2969.tar.xz
dt-bindings: phy: qmp: Add support for QMP phy in IPQ8074
IPQ8074 uses QMP PHY controller that provides support to PCIe and USB. Adding DT binding information for the same. Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings/phy')
-rw-r--r--Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt8
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
index 7dc6c635b71d..b6a9f2b92bab 100644
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -6,6 +6,7 @@ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
Required properties:
- compatible: compatible list, contains:
+ "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
@@ -38,6 +39,8 @@ Required properties:
"phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain
"phy", "common".
+ For "qcom,ipq8074-qmp-pcie-phy" must contain:
+ "phy", "common".
- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
@@ -63,6 +66,11 @@ Required properties for child node:
- clock-output-names: Name of the PHY clock that will be the parent for
the above pipe clock.
+ For "qcom,ipq8074-qmp-pcie-phy":
+ - "pcie20_phy0_pipe_clk" Pipe Clock parent
+ (or)
+ "pcie20_phy1_pipe_clk"
+
- resets: a list of phandles and reset controller specifier pairs,
one for each entry in reset-names.
- reset-names: Must contain following for pcie qmp phys: