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author | Philipp Zabel <p.zabel@pengutronix.de> | 2022-04-07 18:43:29 +0300 |
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committer | Philipp Zabel <p.zabel@pengutronix.de> | 2022-05-03 18:41:29 +0300 |
commit | 7809a619d41e6c1c43fdf15f0531681b36ad31c0 (patch) | |
tree | 688de8837f888675a5e6e9d3ec05e7db07a250af /Documentation/devicetree/bindings/reset/lantiq,reset.yaml | |
parent | e2ac01c199b4a9f2d12b55e1c614eba1f03e0eec (diff) | |
download | linux-7809a619d41e6c1c43fdf15f0531681b36ad31c0.tar.xz |
dt-bindings: reset: lantiq,reset: Convert to yaml
Convert the device tree bindings for the Lantiq XWAY SoC RCU reset
controller to YAML schema to allow participating in DT validation.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220407154338.4190674-5-p.zabel@pengutronix.de
Diffstat (limited to 'Documentation/devicetree/bindings/reset/lantiq,reset.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/reset/lantiq,reset.yaml | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/reset/lantiq,reset.yaml b/Documentation/devicetree/bindings/reset/lantiq,reset.yaml new file mode 100644 index 000000000000..15d65a5dd631 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/lantiq,reset.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/lantiq,reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq XWAY SoC RCU reset controller + +maintainers: + - Martin Blumenstingl <martin.blumenstingl@googlemail.com> + +description: | + This binding describes a reset-controller found on the RCU module on Lantiq + XWAY SoCs. This node has to be a sub node of the Lantiq RCU block. + +properties: + compatible: + enum: + - lantiq,danube-reset + - lantiq,xrx200-reset + + reg: + description: | + Defines the following sets of registers in the parent syscon device + Offset of the reset set register + Offset of the reset status register + maxItems: 2 + + '#reset-cells': + description: | + The first cell takes the reset set bit and the second cell takes the + status bit. + const: 2 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + // On the xRX200 SoCs: + reset0: reset-controller@10 { + compatible = "lantiq,xrx200-reset"; + reg = <0x10 0x04>, <0x14 0x04>; + #reset-cells = <2>; + }; |