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| author | Anup Patel <apatel@ventanamicro.com> | 2023-09-25 12:16:25 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-10-12 16:13:48 +0300 |
| commit | 00c6f39c8247b0a5ddca4586d43aec1af7cbccb6 (patch) | |
| tree | 06de8fb6b505792c75ed97a0f4fbc5a43d438909 /Documentation/devicetree/bindings/riscv | |
| parent | 662a601aa355c6917ed2bc1c4e316a4c0ee206ed (diff) | |
| download | linux-00c6f39c8247b0a5ddca4586d43aec1af7cbccb6.tar.xz | |
dt-bindings: riscv: Add Zicond extension entry
Add an entry for the Zicond extension to the riscv,isa-extensions property.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/extensions.yaml | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 36ff6749fbba..c91ab0e46648 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -218,6 +218,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 95cf1f9 + ("Add changes requested by Ved during signoff") of riscv-zicond. + - const: zicsr description: | The standard Zicsr extension for control and status register |