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authorMayuresh Chitale <mchitale@ventanamicro.com>2023-09-13 19:39:00 +0300
committerAnup Patel <anup@brainfault.org>2023-10-12 16:12:46 +0300
commita4f5f39849f39f62f5d4e88cbb600f95f927003d (patch)
treeabcd3bdbedc5b121ba28b15da187d35c09bbae88 /Documentation/devicetree/bindings/riscv
parent9dbaf381008dfa2fad6225633004f7adb1bac252 (diff)
downloadlinux-a4f5f39849f39f62f5d4e88cbb600f95f927003d.tar.xz
dt-bindings: riscv: Add smstateen entry
Add an entry for the Smstateen extension to the riscv,isa-extensions property. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'Documentation/devicetree/bindings/riscv')
-rw-r--r--Documentation/devicetree/bindings/riscv/extensions.yaml6
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index cc1f546fdbdc..36ff6749fbba 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -128,6 +128,12 @@ properties:
changes to interrupts as frozen at commit ccbddab ("Merge pull
request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
+ - const: smstateen
+ description: |
+ The standard Smstateen extension for controlling access to CSRs
+ added by other RISC-V extensions in H/S/VS/U/VU modes and as
+ ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
+
- const: ssaia
description: |
The standard Ssaia supervisor-level extension for the advanced