diff options
author | Olof Johansson <olof@lixom.net> | 2018-01-12 21:16:17 +0300 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2018-01-12 21:16:17 +0300 |
commit | c9f6603662a1a6a3a2613c09632f5b9497f6e6a4 (patch) | |
tree | 08ea32b7064d9ab3386806ec19121e213f0849ed /Documentation/devicetree/bindings/soc | |
parent | ffdc98c4f25b1f4fb96cd9190917b53a760f3fec (diff) | |
parent | cee8113a295acfc4cd25728d7c3d44e6bc3bbff9 (diff) | |
download | linux-c9f6603662a1a6a3a2613c09632f5b9497f6e6a4.tar.xz |
Merge tag 'zynqmp-soc-for-4.16' of https://github.com/Xilinx/linux-xlnx into next/drivers
arm: Xilinx ZynqMP SoC patches for v4.16
- Create drivers/soc/xilinx folder structure
- Add ZynqMP vcu init driver
* tag 'zynqmp-soc-for-4.16' of https://github.com/Xilinx/linux-xlnx:
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver
soc: xilinx: Create folder structure for soc specific drivers
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'Documentation/devicetree/bindings/soc')
-rw-r--r-- | Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt new file mode 100644 index 000000000000..6786d6715df0 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt @@ -0,0 +1,31 @@ +LogicoreIP designed compatible with Xilinx ZYNQ family. +------------------------------------------------------- + +General concept +--------------- + +LogicoreIP design to provide the isolation between processing system +and programmable logic. Also provides the list of register set to configure +the frequency. + +Required properties: +- compatible: shall be one of: + "xlnx,vcu" + "xlnx,vcu-logicoreip-1.0" +- reg, reg-names: There are two sets of registers need to provide. + 1. vcu slcr + 2. Logicore + reg-names should contain name for the each register sequence. +- clocks: phandle for aclk and pll_ref clocksource +- clock-names: The identification string, "aclk", is always required for + the axi clock. "pll_ref" is required for pll. +Example: + + xlnx_vcu: vcu@a0040000 { + compatible = "xlnx,vcu-logicoreip-1.0"; + reg = <0x0 0xa0040000 0x0 0x1000>, + <0x0 0xa0041000 0x0 0x1000>; + reg-names = "vcu_slcr", "logicore"; + clocks = <&si570_1>, <&clkc 71>; + clock-names = "pll_ref", "aclk"; + }; |