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author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-11-13 20:43:24 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-11-13 20:43:24 +0300 |
commit | e75427c6945460c36bfcab4cd33db0adc0e17200 (patch) | |
tree | b6ffdc7b7a7de951681e900ee0ce7c405864b4b3 /Documentation/devicetree/bindings/spi/spi-sprd-adi.txt | |
parent | 5f194bf4853bcb6e7442518b70fb20a875ed34f0 (diff) | |
parent | abbdb5ce31c21a4b3c3922c56030f3d487497933 (diff) | |
download | linux-e75427c6945460c36bfcab4cd33db0adc0e17200.tar.xz |
Merge tag 'spi-v4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"This release is almost entirely driver changes, there's a couple of
fixes in the core but otherwise it's all drivers:
- fix for mixed dynamic and static bus number assignment.
- fixes for some leaks arising from confusing lifetime rules during
device unregistration and improved documentation to try to help
avoid this in the future.
- fixes to make the native chip select support for i.MX usable.
- slave mode support for i.MX.
- support for Coldfire MCF5441x DSPI, Renesas R8A7443/5 and
Spreadtrum ADI"
* tag 'spi-v4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (31 commits)
spi: imx: Don't require platform data chipselect array
spi: imx: Fix failure path leak on GPIO request error
spi: imx: GPIO based chip selects should not be required
spi: sh-msiof: remove redundant pointer dev
spi: s3c64xx: remove redundant pointer sci
spi: spi-fsl-dspi: enabling Coldfire mcf5441x dspi
spi: fix IDR collision on systems with both fixed and dynamic SPI bus numbers
spi: orion: remove redundant assignment of status to zero
spi: sh-msiof: Fix DMA transfer size check
spi: imx: Fix failure path leak on GPIO request error
spi: spi-axi: fix potential use-after-free after deregistration
spi: document odd controller reference handling
spi: fix use-after-free at controller deregistration
spi: sprd: Fix the possible negative value of BIT()
spi: sprd-adi: fix platform_no_drv_owner.cocci warnings
spi: a3700: Change SPI mode before asserting chip-select
spi: tegra114: correct register name in definition
spi: spreadtrum adi: add hwspinlock dependency
spi: sh-msiof: Use of_device_get_match_data() helper
spi: rspi: Use of_device_get_match_data() helper
...
Diffstat (limited to 'Documentation/devicetree/bindings/spi/spi-sprd-adi.txt')
-rw-r--r-- | Documentation/devicetree/bindings/spi/spi-sprd-adi.txt | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt b/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt new file mode 100644 index 000000000000..8de589b376ce --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-sprd-adi.txt @@ -0,0 +1,58 @@ +Spreadtrum ADI controller + +ADI is the abbreviation of Anolog-Digital interface, which is used to access +analog chip (such as PMIC) from digital chip. ADI controller follows the SPI +framework for its hardware implementation is alike to SPI bus and its timing +is compatile to SPI timing. + +ADI controller has 50 channels including 2 software read/write channels and +48 hardware channels to access analog chip. For 2 software read/write channels, +users should set ADI registers to access analog chip. For hardware channels, +we can configure them to allow other hardware components to use it independently, +which means we can just link one analog chip address to one hardware channel, +then users can access the mapped analog chip address by this hardware channel +triggered by hardware components instead of ADI software channels. + +Thus we introduce one property named "sprd,hw-channels" to configure hardware +channels, the first value specifies the hardware channel id which is used to +transfer data triggered by hardware automatically, and the second value specifies +the analog chip address where user want to access by hardware components. + +Since we have multi-subsystems will use unique ADI to access analog chip, when +one system is reading/writing data by ADI software channels, that should be under +one hardware spinlock protection to prevent other systems from reading/writing +data by ADI software channels at the same time, or two parallel routine of setting +ADI registers will make ADI controller registers chaos to lead incorrect results. +Then we need one hardware spinlock to synchronize between the multiple subsystems. + +Required properties: +- compatible: Should be "sprd,sc9860-adi". +- reg: Offset and length of ADI-SPI controller register space. +- hwlocks: Reference to a phandle of a hwlock provider node. +- hwlock-names: Reference to hwlock name strings defined in the same order + as the hwlocks, should be "adi". +- #address-cells: Number of cells required to define a chip select address + on the ADI-SPI bus. Should be set to 1. +- #size-cells: Size of cells required to define a chip select address size + on the ADI-SPI bus. Should be set to 0. + +Optional properties: +- sprd,hw-channels: This is an array of channel values up to 49 channels. + The first value specifies the hardware channel id which is used to + transfer data triggered by hardware automatically, and the second + value specifies the analog chip address where user want to access + by hardware components. + +SPI slave nodes must be children of the SPI controller node and can contain +properties described in Documentation/devicetree/bindings/spi/spi-bus.txt. + +Example: + adi_bus: spi@40030000 { + compatible = "sprd,sc9860-adi"; + reg = <0 0x40030000 0 0x10000>; + hwlocks = <&hwlock1 0>; + hwlock-names = "adi"; + #address-cells = <1>; + #size-cells = <0>; + sprd,hw-channels = <30 0x8c20>; + }; |