diff options
author | Noam Camus <noamca@mellanox.com> | 2016-11-17 10:12:43 +0300 |
---|---|---|
committer | Vineet Gupta <vgupta@synopsys.com> | 2016-11-30 22:54:25 +0300 |
commit | 60263dcd821b9558ea08b112d9d31ffbe3ac643f (patch) | |
tree | f77ab6f38364a802f839b6ec310bbafd4837df3b /Documentation/devicetree/bindings/timer | |
parent | 0465fb495f9c9698de08ff103905008e5f38e8f1 (diff) | |
download | linux-60263dcd821b9558ea08b112d9d31ffbe3ac643f.tar.xz |
clocksource: Add clockevent support to NPS400 driver
Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to control clock events per HW thread.
The design idea is that for each core there is dedicated register
(TSI) serving all 16 HW threads.
The register is a bitmask with one bit for each HW thread.
When HW thread wants that next expiration of timer interrupt will
hit it then the proper bit should be set in this dedicated register.
When timer expires all HW threads within this core which their bit
is set at the TSI register will be interrupted.
Driver can be used from device tree by:
compatible = "ezchip,nps400-timer0" <-- for clocksource
compatible = "ezchip,nps400-timer1" <-- for clockevent
Note that name convention for timer0/timer1 was taken from legacy
ARC design. This design is our base before adding HW threads.
For backward compatibility we keep "ezchip,nps400-timer" for clocksource
Signed-off-by: Noam Camus <noamca@mellanox.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/timer')
-rw-r--r-- | Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt | 17 | ||||
-rw-r--r-- | Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt (renamed from Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt) | 6 |
2 files changed, 20 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt new file mode 100644 index 000000000000..e3cfce8fecc5 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt @@ -0,0 +1,17 @@ +NPS Network Processor + +Required properties: + +- compatible : should be "ezchip,nps400-timer0" + +Clocks required for compatible = "ezchip,nps400-timer0": +- interrupts : The interrupt of the first timer +- clocks : Must contain a single entry describing the clock input + +Example: + +timer { + compatible = "ezchip,nps400-timer0"; + interrupts = <3>; + clocks = <&sysclk>; +}; diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt index c8c03d700382..c0ab4190b8fb 100644 --- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt +++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt @@ -2,14 +2,14 @@ NPS Network Processor Required properties: -- compatible : should be "ezchip,nps400-timer" +- compatible : should be "ezchip,nps400-timer1" -Clocks required for compatible = "ezchip,nps400-timer": +Clocks required for compatible = "ezchip,nps400-timer1": - clocks : Must contain a single entry describing the clock input Example: timer { - compatible = "ezchip,nps400-timer"; + compatible = "ezchip,nps400-timer1"; clocks = <&sysclk>; }; |