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author | Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-03-14 16:24:35 +0300 |
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committer | Wim Van Sebroeck <wim@linux-watchdog.org> | 2023-04-22 17:01:47 +0300 |
commit | b24e265d6f0a0965ae0d0a19848544300c397a2e (patch) | |
tree | a5f3413f6855f3d32db7a2713cfa48fd4957cb13 /Documentation/devicetree/bindings/watchdog | |
parent | 819d14135da5f8cd0e2104a6def805707e46d99b (diff) | |
download | linux-b24e265d6f0a0965ae0d0a19848544300c397a2e.tar.xz |
dt-bindings: watchdog: Add watchdog for StarFive JH7100 and JH7110
Add bindings to describe the watchdog for the StarFive JH7100/JH7110 SoC.
And Use JH7100 as first StarFive SoC with watchdog.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20230314132437.121534-2-xingyu.wu@starfivetech.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Diffstat (limited to 'Documentation/devicetree/bindings/watchdog')
-rw-r--r-- | Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml new file mode 100644 index 000000000000..68f3f6fd08a6 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/starfive,jh7100-wdt.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive Watchdog for JH7100 and JH7110 SoC + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + - Samin Guo <samin.guo@starfivetech.com> + +description: + The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog + has only one timeout phase and reboots. And JH7110 watchdog has two + timeout phases. At the first phase, the signal of watchdog interrupt + output(WDOGINT) will rise when counter is 0. The counter will reload + the timeout value. And then, if counter decreases to 0 again and WDOGINT + isn't cleared, the watchdog will reset the system unless the watchdog + reset is disabled. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - starfive,jh7100-wdt + - starfive,jh7110-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: APB clock + - description: Core clock + + clock-names: + items: + - const: apb + - const: core + + resets: + items: + - description: APB reset + - description: Core reset + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + watchdog@12480000 { + compatible = "starfive,jh7100-wdt"; + reg = <0x12480000 0x10000>; + clocks = <&clk 171>, + <&clk 172>; + clock-names = "apb", "core"; + resets = <&rst 99>, + <&rst 100>; + }; |