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author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2022-11-15 18:27:19 +0300 |
---|---|---|
committer | Will Deacon <will@kernel.org> | 2023-01-24 14:35:52 +0300 |
commit | 6bc6af375c7025663fbc36bcb7e91f3af653742b (patch) | |
tree | 7500c3a412530237dff4c856b6cd28f786f8364f /Documentation/devicetree/bindings | |
parent | 142e821f68cf5da79ce722cb9c1323afae30e185 (diff) | |
download | linux-6bc6af375c7025663fbc36bcb7e91f3af653742b.tar.xz |
dt-bindings: arm-smmu: Allow 3 power domains on SM6375 MMU500
The SMMU on SM6375 requires 3 power domains to be active. Add an
appropriate description of that.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20221115152727.9736-2-konrad.dybcio@linaro.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r-- | Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index b28c5c2b0ff2..895ec8418465 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -201,7 +201,8 @@ properties: maxItems: 7 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 nvidia,memory-controller: description: | @@ -366,6 +367,26 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + - if: + properties: + compatible: + contains: + const: qcom,sm6375-smmu-500 + then: + properties: + power-domains: + items: + - description: SNoC MMU TBU RT GDSC + - description: SNoC MMU TBU NRT GDSC + - description: SNoC TURING MMU TBU0 GDSC + + required: + - power-domains + else: + properties: + power-domains: + maxItems: 1 + examples: - |+ /* SMMU with stream matching or stream indexing */ |