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author | Stephen Boyd <sboyd@kernel.org> | 2024-01-09 22:52:35 +0300 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2024-01-09 22:52:35 +0300 |
commit | 8066514dc53dd649be6b24a7a92c3602d42357d7 (patch) | |
tree | 067515a7ecff3e06a8e170a95e780faebdc36414 /Documentation/devicetree | |
parent | 76a2ee33762e18eef15f2677f70b251a1839f0c5 (diff) | |
parent | b08fa385937c1b6baae24683f6430230212b43e5 (diff) | |
parent | b2adbc9cea752539f6421e9d4642408f666c1251 (diff) | |
parent | 5e3b5f31fc2c434d97f10f1facc3f08355adefee (diff) | |
parent | 4287cd628f77de6ddaa1f458274a5337f373b040 (diff) | |
parent | 5a72f0711151b5ccdd14e22ff5f2ba3605483a95 (diff) | |
download | linux-8066514dc53dd649be6b24a7a92c3602d42357d7.tar.xz |
Merge branches 'clk-versa', 'clk-silabs', 'clk-samsung', 'clk-starfive' and 'clk-sophgo' into clk-next
- Add glitch free PLL setting support to si5351 clk driver
* clk-versa:
clk: versaclock3: Drop ret variable
clk: versaclock3: Add missing space between ')' and '{'
clk: versaclock3: Use u8 return type for get_parent() callback
clk: versaclock3: Avoid unnecessary padding
clk: versaclock3: Update vc3_get_div() to avoid divide by zero
* clk-silabs:
clk: si5351: allow PLLs to be adjusted without reset
dt-bindings: clock: si5351: add PLL reset mode property
dt-bindings: clock: si5351: convert to yaml
* clk-samsung:
clk: samsung: Improve kernel-doc comments
clk: samsung: Fix kernel-doc comments
* clk-starfive:
clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx
clk: starfive: Add flags argument to JH71X0__MUX macro
* clk-sophgo:
dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC