Merge branch 'pci/controller/rockchip'

- Remove writes to unused registers (Rick Wertenbroek)

- Write endpoint Device ID using correct register (Rick Wertenbroek)

- Assert PCI Configuration Enable bit after probe so endpoint responds
  instead of generating Request Retry Status messages (Rick Wertenbroek)

- Poll waiting for PHY PLLs to lock (Rick Wertenbroek)

- Update RK3399 example DT binding to be valid (Rick Wertenbroek)

- Use RK3399 PCIE_CLIENT_LEGACY_INT_CTRL to generate INTx instead of
  manually generating PCIe message (Rick Wertenbroek)

- Use multiple windows to avoid address translation conflicts (Rick
  Wertenbroek)

- Use u32 (not u16) when accessing 32-bit registers (Rick Wertenbroek)

- Hide MSI-X Capability, since RK3399 can't generate MSI-X (Rick
  Wertenbroek)

- Set endpoint controller required alignment to 256 (Damien Le Moal)

* pci/controller/rockchip:
  PCI: rockchip: Set address alignment for endpoint mode
  PCI: rockchip: Don't advertise MSI-X in PCIe capabilities
  PCI: rockchip: Use u32 variable to access 32-bit registers
  PCI: rockchip: Fix window mapping and address translation for endpoint
  PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core
  dt-bindings: PCI: Update the RK3399 example to a valid one
  PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked
  PCI: rockchip: Assert PCI Configuration Enable bit after probe
  PCI: rockchip: Write PCI Device ID to correct register
  PCI: rockchip: Remove writes to unused registers

1 files changed, 3 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
index 88386a6d7011..6b62f6f58efe 100644
--- a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
@@ -47,7 +47,7 @@ examples:
 
         pcie-ep@f8000000 {
             compatible = "rockchip,rk3399-pcie-ep";
-            reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
+            reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>;
             reg-names = "apb-base", "mem-base";
             clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
               <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
@@ -63,6 +63,8 @@ examples:
             phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
             phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
             rockchip,max-outbound-regions = <16>;
+            pinctrl-names = "default";
+            pinctrl-0 = <&pcie_clkreqnb_cpm>;
         };
     };
 ...