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| author | Marc Zyngier <maz@kernel.org> | 2022-03-10 11:59:03 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-03-10 11:59:03 +0300 |
| commit | c425060a406c941a9e17bfe578f57cc707b46b3c (patch) | |
| tree | b50d71a3e108a5dbd892fdbd617d5c2151986893 /Documentation | |
| parent | 92af5d479013494ad15f929ef0b75b705c34fbb4 (diff) | |
| parent | dc29812dbc873ae00bf19a4b8661984d7cce7a2e (diff) | |
| download | linux-c425060a406c941a9e17bfe578f57cc707b46b3c.tar.xz | |
Merge branch irq/aic-pmu into irq/irqchip-next
* irq/aic-pmu:
: .
: Prefix branch for the M1 PMU support, adding the required
: irqchip changes. Shared with the arm64 tree.
: .
irqchip/apple-aic: Fix cpumask allocation for FIQs
irqchip/apple-aic: Move PMU-specific registers to their own include file
arm64: dts: apple: Add t8303 PMU nodes
arm64: dts: apple: Add t8103 PMU interrupt affinities
irqchip/apple-aic: Wire PMU interrupts
irqchip/apple-aic: Parse FIQ affinities from device-tree
dt-bindings: apple,aic: Add affinity description for per-cpu pseudo-interrupts
dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts
dt-bindings: arm-pmu: Document Apple PMU compatible strings
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/pmu.yaml | 2 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml | 31 |
2 files changed, 33 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index 981bac451698..7a04b8aaaec3 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,6 +20,8 @@ properties: items: - enum: - apm,potenza-pmu + - apple,firestorm-pmu + - apple,icestorm-pmu - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu - arm,arm1176-pmu diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml index 97359024709a..85c85b694217 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -56,6 +56,8 @@ properties: - 1: virtual HV timer - 2: physical guest timer - 3: virtual guest timer + - 4: 'efficient' CPU PMU + - 5: 'performance' CPU PMU The 3rd cell contains the interrupt flags. This is normally IRQ_TYPE_LEVEL_HIGH (4). @@ -68,6 +70,35 @@ properties: power-domains: maxItems: 1 + affinities: + type: object + additionalProperties: false + description: + FIQ affinity can be expressed as a single "affinities" node, + containing a set of sub-nodes, one per FIQ with a non-default + affinity. + patternProperties: + "^.+-affinity$": + type: object + additionalProperties: false + properties: + apple,fiq-index: + description: + The interrupt number specified as a FIQ, and for which + the affinity is not the default. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 5 + + cpus: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Should be a list of phandles to CPU nodes (as described in + Documentation/devicetree/bindings/arm/cpus.yaml). + + required: + - fiq-index + - cpus + required: - compatible - '#interrupt-cells' |