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authorVineet Gupta <vgupta@synopsys.com>2017-01-18 23:59:21 +0300
committerVineet Gupta <vgupta@synopsys.com>2017-01-19 01:52:43 +0300
commite497c8e52a83ebb5309ab41c8851c9cb53f28b73 (patch)
tree09224d6a1274b9c74ebd8845486af8dd6e39b113 /arch/arc/mm/cache.c
parent8c47f83ba45928ce9495fcf1b29e828c28e3c839 (diff)
downloadlinux-e497c8e52a83ebb5309ab41c8851c9cb53f28b73.tar.xz
ARCv2: IOC: Use actual memory size to setup aperture size
vs. fixed 512M before. But this still assumes that all of memory is under IOC which may not be true for the SoC. Improve that later when this becomes a real issue, by specifying this from DT. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/mm/cache.c')
-rw-r--r--arch/arc/mm/cache.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 1b4cda10844a..3c275a81528c 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -995,6 +995,8 @@ SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
*/
noinline void arc_ioc_setup(void)
{
+ unsigned int ap_sz;
+
/* Flush + invalidate + disable L1 dcache */
__dc_disable();
@@ -1005,8 +1007,14 @@ noinline void arc_ioc_setup(void)
/* IOC Aperture start: TDB: handle non default CONFIG_LINUX_LINK_BASE */
write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
- /* IOC Aperture size: TBD: handle different mem sizes, PAE... */
- write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, 0x11);
+ /*
+ * IOC Aperture size:
+ * decoded as 2 ^ (SIZE + 2) KB: so setting 0x11 implies 512M
+ * TBD: fix for PGU + 1GB of low mem
+ * TBD: fix for PAE
+ */
+ ap_sz = order_base_2(arc_get_mem_sz()/1024) - 2;
+ write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, ap_sz);
write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);