diff options
author | Rafał Miłecki <rafal@milecki.pl> | 2023-05-15 18:19:20 +0300 |
---|---|---|
committer | Florian Fainelli <florian.fainelli@broadcom.com> | 2023-05-23 19:29:13 +0300 |
commit | b3b3cd885ed39cb4b38319a1c4fa4e41db6fee72 (patch) | |
tree | 922749965f251e844684b88f79246ba39e63a323 /arch/arm/boot/dts/bcm5301x.dtsi | |
parent | 4eaa40bdabff8f5be634f151f8e564a8976f0572 (diff) | |
download | linux-b3b3cd885ed39cb4b38319a1c4fa4e41db6fee72.tar.xz |
ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ / MIT
Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing.
That syncs more Northstar code to be based on the same licensing schema.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Link: https://lore.kernel.org/r/20230515151921.25021-1-zajec5@gmail.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
Diffstat (limited to 'arch/arm/boot/dts/bcm5301x.dtsi')
-rw-r--r-- | arch/arm/boot/dts/bcm5301x.dtsi | 85 |
1 files changed, 0 insertions, 85 deletions
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index bc36edc24510..d6c31ead0398 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -11,41 +11,7 @@ #include "bcm-ns.dtsi" / { - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&gic>; - - chipcommon-a-bus@18000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x18000000 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - - uart0: serial@300 { - compatible = "ns16550"; - reg = <0x0300 0x100>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&iprocslow>; - status = "disabled"; - }; - - uart1: serial@400 { - compatible = "ns16550"; - reg = <0x0400 0x100>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&iprocslow>; - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_uart1>; - status = "disabled"; - }; - }; - mpcore-bus@19000000 { - compatible = "simple-bus"; - ranges = <0x00000000 0x19000000 0x00023000>; - #address-cells = <1>; - #size-cells = <1>; - a9pll: arm_clk@0 { #clock-cells = <0>; compatible = "brcm,nsp-armpll"; @@ -53,26 +19,6 @@ reg = <0x00000 0x1000>; }; - scu@20000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x20000 0x100>; - }; - - timer@20200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20200 0x100>; - interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; - clocks = <&periph_clk>; - }; - - timer@20600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20600 0x20>; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | - IRQ_TYPE_EDGE_RISING)>; - clocks = <&periph_clk>; - }; - watchdog@20620 { compatible = "arm,cortex-a9-twd-wdt"; reg = <0x20620 0x20>; @@ -80,25 +26,6 @@ IRQ_TYPE_EDGE_RISING)>; clocks = <&periph_clk>; }; - - gic: interrupt-controller@21000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x21000 0x1000>, - <0x20100 0x100>; - }; - - L2: cache-controller@22000 { - compatible = "arm,pl310-cache"; - reg = <0x22000 0x1000>; - cache-unified; - arm,shared-override; - prefetch-data = <1>; - prefetch-instr = <1>; - cache-level = <2>; - }; }; pmu { @@ -301,18 +228,6 @@ }; }; - nand_controller: nand-controller@18028000 { - compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; - reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; - reg-names = "nand", "iproc-idm", "iproc-ext"; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - - #address-cells = <1>; - #size-cells = <0>; - - brcm,nand-has-wp; - }; - spi@18029200 { compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; reg = <0x18029200 0x184>, |