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authorOndrej Jirman <megous@megous.com>2019-04-01 16:36:10 +0300
committerMaxime Ripard <maxime.ripard@bootlin.com>2019-04-01 17:31:41 +0300
commit3764db4f0b4eefbf4aa97ef7255ae3c29b56ee8c (patch)
treef1d845e3202120347c8e8c7a86db9cabe799325e /arch/arm/boot/dts/sun8i-a83t.dtsi
parent31ec8c14566e2bad88a71daf209d2caf80036a3e (diff)
downloadlinux-3764db4f0b4eefbf4aa97ef7255ae3c29b56ee8c.tar.xz
ARM: dts: sun8i: a83t: Add missing CPU clock references
A83T DTSI has cpu clocks defined only on the first CPU in each cluster. We can bring down any CPU in the cluster, so we need to define clock for each CPU, so that the system knows what clock to use if the first CPU is down. Also move the clocks property below the compatible on cpus where it is already defined. Property "clock-names" is not needed. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a83t.dtsi')
-rw-r--r--arch/arm/boot/dts/sun8i-a83t.dtsi12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 59a48ce26fec..f739b88efb53 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -61,10 +61,9 @@
#size-cells = <0>;
cpu0: cpu@0 {
- clocks = <&ccu CLK_C0CPUX>;
- clock-names = "cpu";
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C0CPUX>;
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
@@ -75,6 +74,7 @@
cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C0CPUX>;
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
@@ -85,6 +85,7 @@
cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C0CPUX>;
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
@@ -95,6 +96,7 @@
cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C0CPUX>;
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
@@ -103,10 +105,9 @@
};
cpu100: cpu@100 {
- clocks = <&ccu CLK_C1CPUX>;
- clock-names = "cpu";
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C1CPUX>;
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
@@ -117,6 +118,7 @@
cpu@101 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C1CPUX>;
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
@@ -127,6 +129,7 @@
cpu@102 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C1CPUX>;
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
@@ -137,6 +140,7 @@
cpu@103 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C1CPUX>;
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";