diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2023-12-06 16:55:38 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-12-16 08:19:01 +0300 |
| commit | 07299ba2e7d98045e6b522f7c5b97f402b15bc82 (patch) | |
| tree | b703a318facc476901de5f852943845e32230935 /arch/arm/boot | |
| parent | fc209f869310776c437daba478246df64d82c38b (diff) | |
| download | linux-07299ba2e7d98045e6b522f7c5b97f402b15bc82.tar.xz | |
ARM: dts: qcom: Use "pcie" as the node name instead of "pci"
Qcom SoCs doesn't support the legacy PCI, but only PCIe. So use the correct
node name for the controller instances.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20231206135540.17068-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 6 |
4 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 95ac25e1a3b4..3faf57035d54 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -1284,7 +1284,7 @@ qcom,ncb = <3>; }; - pcie: pci@1b500000 { + pcie: pcie@1b500000 { compatible = "qcom,pcie-apq8064"; reg = <0x1b500000 0x1000>, <0x1b502000 0x80>, diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi index 468ebc40d2ad..374af6dd360a 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019-ap.dk04.1.dtsi @@ -98,7 +98,7 @@ }; }; - pci@40000000 { + pcie@40000000 { status = "okay"; perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 9844e0b7cff9..6cbbccda5cf5 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -417,7 +417,7 @@ reg = <0x4ab000 0x4>; }; - pcie0: pci@40000000 { + pcie0: pcie@40000000 { compatible = "qcom,pcie-ipq4019"; reg = <0x40000000 0xf1d>, <0x40000f20 0xa8>, diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index c3677440b786..6a7f4dd0f775 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -1076,7 +1076,7 @@ status = "disabled"; }; - pcie0: pci@1b500000 { + pcie0: pcie@1b500000 { compatible = "qcom,pcie-ipq8064"; reg = <0x1b500000 0x1000 0x1b502000 0x80 @@ -1127,7 +1127,7 @@ perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; }; - pcie1: pci@1b700000 { + pcie1: pcie@1b700000 { compatible = "qcom,pcie-ipq8064"; reg = <0x1b700000 0x1000 0x1b702000 0x80 @@ -1178,7 +1178,7 @@ perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; }; - pcie2: pci@1b900000 { + pcie2: pcie@1b900000 { compatible = "qcom,pcie-ipq8064"; reg = <0x1b900000 0x1000 0x1b902000 0x80 |