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| author | Arnd Bergmann <arnd@arndb.de> | 2024-01-02 12:51:38 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2024-01-02 12:51:39 +0300 |
| commit | 2f5ed2cacc1125e5b48677b92a445761c2ca8e4e (patch) | |
| tree | cc70fe0b910f7e59d0a0f2fb8bf28b7beac9397d /arch/arm/boot | |
| parent | 1e672c2585ee3ef13695d5936cc59a0d73143fc0 (diff) | |
| parent | cc6fc55c7ae04ab19b3972f78d3a8b1be32bf533 (diff) | |
| download | linux-2f5ed2cacc1125e5b48677b92a445761c2ca8e4e.tar.xz | |
Merge tag 'qcom-arm32-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
A few more Qualcomm Arm32 DeviceTree updates fr v6.8
The recently introduced changes to the SDX55 USB controller interrupt
flags prevents the USB controller from probing. These patches corrects
the PDC's interrupt-cells, so that appropriate interrupt controller
(which supports both-edge interrupts) can be used instead, which
resolves the issue.
The SDX55 PCIe PHY base address is also adjusted, from a mistake when
the node recently was transitioned to the modernized DeviceTree binding.
* tag 'qcom-arm32-for-6.8-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: sdx55: Fix the base address of PCIe PHY
ARM: dts: qcom: sdx55: fix USB SS wakeup
ARM: dts: qcom: sdx55: fix USB DP/DM HS PHY interrupts
ARM: dts: qcom: sdx55: fix pdc '#interrupt-cells'
Link: https://lore.kernel.org/r/20231231033153.3262575-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 0fe220408888..2045fc779f88 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -431,9 +431,9 @@ status = "disabled"; }; - pcie_phy: phy@1c07000 { + pcie_phy: phy@1c06000 { compatible = "qcom,sdx55-qmp-pcie-phy"; - reg = <0x01c07000 0x2000>; + reg = <0x01c06000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges; @@ -580,10 +580,10 @@ <&gcc GCC_USB30_MASTER_CLK>; assigned-clock-rates = <19200000>, <200000000>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 158 IRQ_TYPE_EDGE_BOTH>, - <GIC_SPI 157 IRQ_TYPE_EDGE_BOTH>; + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 51 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 11 IRQ_TYPE_EDGE_BOTH>, + <&pdc 10 IRQ_TYPE_EDGE_BOTH>; interrupt-names = "hs_phy_irq", "ss_phy_irq", "dm_hs_phy_irq", "dp_hs_phy_irq"; @@ -607,7 +607,7 @@ compatible = "qcom,sdx55-pdc", "qcom,pdc"; reg = <0x0b210000 0x30000>; qcom,pdc-ranges = <0 179 52>; - #interrupt-cells = <3>; + #interrupt-cells = <2>; interrupt-parent = <&intc>; interrupt-controller; }; |