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author | Amit Daniel Kachhap <amit.kachhap@arm.com> | 2022-11-17 09:05:19 +0300 |
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committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2022-11-28 14:57:35 +0300 |
commit | 3bda6d88489769fba5672dc66debdc1f5516c5fe (patch) | |
tree | 3ee41cfa8dc802880cc0fb368e9027aa272e751a /arch/arm/kernel | |
parent | 956ca3a4eb81c1b8cc3226af3083847544dcb098 (diff) | |
download | linux-3bda6d88489769fba5672dc66debdc1f5516c5fe.tar.xz |
ARM: 9273/1: Add hwcap for Speculation Barrier(SB)
Speculation Barrier(FEAT_SB) is a feature present in AArch32 state for
Armv8 and is represented by ISAR6.SB identification register.
This feature denotes the presence of SB instruction and hence adding a
hwcap will enable the userspace to check it before trying to use this
instruction.
This commit adds the ID feature bit detection, and uses elf_hwcap2
accordingly.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/kernel')
-rw-r--r-- | arch/arm/kernel/setup.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 5807fa021785..979612add87a 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -450,6 +450,7 @@ static void __init cpuid_init_hwcaps(void) { int block; u32 isar5; + u32 isar6; if (cpu_architecture() < CPU_ARCH_ARMv7) return; @@ -485,6 +486,12 @@ static void __init cpuid_init_hwcaps(void) block = cpuid_feature_extract_field(isar5, 16); if (block >= 1) elf_hwcap2 |= HWCAP2_CRC32; + + /* Check for Speculation barrier instruction */ + isar6 = read_cpuid_ext(CPUID_EXT_ISAR6); + block = cpuid_feature_extract_field(isar6, 12); + if (block >= 1) + elf_hwcap2 |= HWCAP2_SB; } static void __init elf_hwcap_fixup(void) @@ -1264,6 +1271,7 @@ static const char *hwcap2_str[] = { "sha1", "sha2", "crc32", + "sb", NULL }; |