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author | Amit Daniel Kachhap <amit.kachhap@arm.com> | 2022-11-17 09:10:35 +0300 |
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committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2022-11-28 14:57:35 +0300 |
commit | fea53546be574f2e357fa53f4a582788b20f283c (patch) | |
tree | f110f255ff0de307f0195c60be74e9fd96c387ba /arch/arm/kernel | |
parent | 3bda6d88489769fba5672dc66debdc1f5516c5fe (diff) | |
download | linux-fea53546be574f2e357fa53f4a582788b20f283c.tar.xz |
ARM: 9274/1: Add hwcap for Speculative Store Bypassing Safe
Speculative Store Bypassing Safe(FEAT_SSBS) is a feature present in
AArch32 state for Armv8 and is represented by ID_PFR2_EL1.SSBS
identification register.
This feature denotes the presence of PSTATE.ssbs bit and hence adding a
hwcap will enable the userspace to check it before trying to set/unset
this PSTATE.
This commit adds the ID feature bit detection, and uses elf_hwcap2
accordingly.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/kernel')
-rw-r--r-- | arch/arm/kernel/setup.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 979612add87a..4ec3ec32d830 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -451,6 +451,7 @@ static void __init cpuid_init_hwcaps(void) int block; u32 isar5; u32 isar6; + u32 pfr2; if (cpu_architecture() < CPU_ARCH_ARMv7) return; @@ -492,6 +493,12 @@ static void __init cpuid_init_hwcaps(void) block = cpuid_feature_extract_field(isar6, 12); if (block >= 1) elf_hwcap2 |= HWCAP2_SB; + + /* Check for Speculative Store Bypassing control */ + pfr2 = read_cpuid_ext(CPUID_EXT_PFR2); + block = cpuid_feature_extract_field(pfr2, 4); + if (block >= 1) + elf_hwcap2 |= HWCAP2_SSBS; } static void __init elf_hwcap_fixup(void) @@ -1272,6 +1279,7 @@ static const char *hwcap2_str[] = { "sha2", "crc32", "sb", + "ssbs", NULL }; |