summaryrefslogtreecommitdiff
path: root/arch/arm/mm/proc-v7-3level.S
diff options
context:
space:
mode:
authorWill Deacon <will.deacon@arm.com>2013-07-15 17:26:19 +0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2013-07-22 17:29:09 +0400
commitbf3f0f332f76a85ff3a0b393aaded5a8533769c0 (patch)
treec2af37fb279885a29863ec1da7980f16976e8f21 /arch/arm/mm/proc-v7-3level.S
parentb6992fa9a74862c5addb62cde1657c7479615d86 (diff)
downloadlinux-bf3f0f332f76a85ff3a0b393aaded5a8533769c0.tar.xz
ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2
Commit ae8a8b9553bd ("ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead") added early function returns for page table cache flushing operations on ARMv7 SMP CPUs. Unfortunately, when targetting Thumb-2, these `mov pc, lr' sequences assemble to 2 bytes which can lead to corruption of the instruction stream after code patching. This patch fixes the alternates to use wide (32-bit) instructions for Thumb-2, therefore ensuring that the patching code works correctly. Cc: <stable@vger.kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v7-3level.S')
-rw-r--r--arch/arm/mm/proc-v7-3level.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index c36ac69488c8..01a719e18bb0 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -81,7 +81,7 @@ ENTRY(cpu_v7_set_pte_ext)
tst r3, #1 << (55 - 32) @ L_PTE_DIRTY
orreq r2, #L_PTE_RDONLY
1: strd r2, r3, [r0]
- ALT_SMP(mov pc, lr)
+ ALT_SMP(W(nop))
ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
#endif
mov pc, lr