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author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-04-22 01:31:39 +0300 |
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committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-05-16 19:26:52 +0300 |
commit | 0022cec7edecd5ea6796dfe0d75330c55dd07a67 (patch) | |
tree | e4bf015aa5e38861b77891996c88b31842d00928 /arch/arm64/boot/dts/apm | |
parent | 7c4f1f1830648bbdce02b13ff5f215c7400e7ea0 (diff) | |
download | linux-0022cec7edecd5ea6796dfe0d75330c55dd07a67.tar.xz |
arm64: dts: apm: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified and cache-level properties to fix warnings like:
apm-mustang.dtb: l2-cache-0: 'cache-level' is a required property
apm-mustang.dtb: l2-cache-0: 'cache-unified' is a required property
Link: https://lore.kernel.org/r/20230421223139.115044-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/apm')
-rw-r--r-- | arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 8 | ||||
-rw-r--r-- | arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 |
2 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 70a10bcafcff..377660d705d1 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -97,15 +97,23 @@ }; xgene_L2_0: l2-cache-0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_1: l2-cache-1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_2: l2-cache-2 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_3: l2-cache-3 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index d73e809fe41a..efa79209f4b2 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -81,15 +81,23 @@ }; xgene_L2_0: l2-cache-0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_1: l2-cache-1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_2: l2-cache-2 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_3: l2-cache-3 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; |