diff options
| author | Nícolas F. R. A. Prado <nfraprado@collabora.com> | 2022-06-29 18:59:56 +0300 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2022-07-07 17:39:18 +0300 |
| commit | b0e50a1f5d240bc71ffc2dbdca9cc986bc370279 (patch) | |
| tree | 380e660cdd4bf81207492d47f6d17b0011aadf72 /arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | |
| parent | b10e80b173b608a36b2d799272884c87c054530e (diff) | |
| download | linux-b0e50a1f5d240bc71ffc2dbdca9cc986bc370279.tar.xz | |
arm64: dts: mediatek: asurada: Add SPI NOR flash memory
Add support for the SPI NOR flash memory present on the Asurada
platform.
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20220629155956.1138955-20-nfraprado@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index a5625b3cb317..4b314435f8fd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -241,6 +241,23 @@ mediatek,mic-type-2 = <2>; /* DMIC */ }; +&nor_flash { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&nor_flash_pins>; + assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6_D8>; + + flash@0 { + compatible = "winbond,w25q64jwm", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; @@ -658,6 +675,29 @@ }; }; + nor_flash_pins: nor-flash-default-pins { + pins-cs-io1 { + pinmux = <PINMUX_GPIO24__FUNC_SPINOR_CS>, + <PINMUX_GPIO28__FUNC_SPINOR_IO1>; + input-enable; + bias-pull-up; + drive-strength = <10>; + }; + + pins-io0 { + pinmux = <PINMUX_GPIO27__FUNC_SPINOR_IO0>; + bias-pull-up; + drive-strength = <10>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO25__FUNC_SPINOR_CK>; + input-enable; + bias-pull-up; + drive-strength = <10>; + }; + }; + pcie_pins: pcie-default-pins { pins-pcie-wake { pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>; |