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| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-03-27 11:36:36 +0300 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2023-04-02 20:24:25 +0300 |
| commit | 80dd5ca523c5bbef082c31fad67825009bfb04d6 (patch) | |
| tree | 54be832d7a03139306980f5ee9262d8bacfbabfa /arch/arm64/boot/dts/mediatek | |
| parent | 80d9c0734330729210b30a46bd28a40ad48e7256 (diff) | |
| download | linux-80dd5ca523c5bbef082c31fad67825009bfb04d6.tar.xz | |
arm64: dts: mediatek: mt6795: Add SoC power domains
Add power domain tree for various hardware blocks on MT6795.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230327083647.22017-7-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt6795.dtsi | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts/mediatek/mt6795.dtsi index ceb6fc948d8a..d63efb32e6bb 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mediatek,mt6795-clk.h> #include <dt-bindings/pinctrl/mt6795-pinfunc.h> +#include <dt-bindings/power/mt6795-power.h> #include <dt-bindings/reset/mediatek,mt6795-resets.h> / { @@ -264,6 +265,84 @@ #reset-cells = <1>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt6795-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT6795_POWER_DOMAIN_VDEC { + reg = <MT6795_POWER_DOMAIN_VDEC>; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + power-domain@MT6795_POWER_DOMAIN_VENC { + reg = <MT6795_POWER_DOMAIN_VENC>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_VENC_SEL>; + clock-names = "mm", "venc"; + #power-domain-cells = <0>; + }; + power-domain@MT6795_POWER_DOMAIN_ISP { + reg = <MT6795_POWER_DOMAIN_ISP>; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + + power-domain@MT6795_POWER_DOMAIN_MM { + reg = <MT6795_POWER_DOMAIN_MM>; + clocks = <&topckgen CLK_TOP_MM_SEL>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT6795_POWER_DOMAIN_MJC { + reg = <MT6795_POWER_DOMAIN_MJC>; + clocks = <&topckgen CLK_TOP_MM_SEL>, + <&topckgen CLK_TOP_MJC_SEL>; + clock-names = "mm", "mjc"; + #power-domain-cells = <0>; + }; + + power-domain@MT6795_POWER_DOMAIN_AUDIO { + reg = <MT6795_POWER_DOMAIN_AUDIO>; + #power-domain-cells = <0>; + }; + + mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC { + reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>; + clocks = <&clk26m>; + clock-names = "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT6795_POWER_DOMAIN_MFG_2D { + reg = <MT6795_POWER_DOMAIN_MFG_2D>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT6795_POWER_DOMAIN_MFG { + reg = <MT6795_POWER_DOMAIN_MFG>; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + }; + }; + pio: pinctrl@10005000 { compatible = "mediatek,mt6795-pinctrl"; reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; |