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| author | Pierre Gondois <pierre.gondois@arm.com> | 2022-11-07 18:57:16 +0300 |
|---|---|---|
| committer | Vignesh Raghavendra <vigneshr@ti.com> | 2023-01-16 16:31:06 +0300 |
| commit | 880932e657ffc677c1b053a947afa87ffed1b29d (patch) | |
| tree | 354ae066d5b2a4555ea990048ce6a04e70f0b728 /arch/arm64/boot/dts/ti | |
| parent | c48ac0efe6d71050f635b40116ba714961ad9d4c (diff) | |
| download | linux-880932e657ffc677c1b053a947afa87ffed1b29d.tar.xz | |
arm64: dts: Update cache properties for ti
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-24-pierre.gondois@arm.com
Diffstat (limited to 'arch/arm64/boot/dts/ti')
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am625.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am62a7.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am642.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am654.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j7200.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 1 |
7 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index cea2cc7de5dd..acc7f8ab6426 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -146,6 +146,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x40000>; cache-line-size = <64>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi index 331d89fda29d..9734549851c0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a7.dtsi @@ -95,6 +95,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x40000>; cache-line-size = <64>; diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi index 8a76f4821b11..7a6eedea3aae 100644 --- a/arch/arm64/boot/dts/ti/k3-am642.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi @@ -58,6 +58,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x40000>; cache-line-size = <64>; cache-sets = <256>; diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi index a89257900047..4cc329b271ac 100644 --- a/arch/arm64/boot/dts/ti/k3-am654.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi @@ -93,6 +93,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; @@ -102,6 +103,7 @@ L2_1: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x80000>; cache-line-size = <64>; cache-sets = <512>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi index b6da0454cc5b..d74f86b0f622 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi @@ -84,6 +84,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 0e23886c9fd1..6975cae644d9 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -86,6 +86,7 @@ L2_0: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; cache-size = <0x100000>; cache-line-size = <64>; cache-sets = <1024>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi index 7b930a85a29d..78295ee0fee5 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi @@ -69,6 +69,7 @@ L2_0: l2-cache0 { compatible = "cache"; + cache-unified; cache-level = <2>; cache-size = <0x100000>; cache-line-size = <64>; |