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| author | Amit Daniel Kachhap <amit.kachhap@arm.com> | 2023-01-11 08:37:06 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2023-01-20 17:28:36 +0300 |
| commit | 4f2c9bf16a4bc209a674e7b76d8e829b917c7f84 (patch) | |
| tree | b71976d4c36ffca5d4ed61914b0ea00d3d8a007b /arch/arm64/kernel/cpuinfo.c | |
| parent | 2d602aa99abb84c34cc9602c8bd6852895314f74 (diff) | |
| download | linux-4f2c9bf16a4bc209a674e7b76d8e829b917c7f84.tar.xz | |
arm64: Add compat hwcap SSBS
This hwcap was added for 32-bit native arm kernel by commit fea53546be57
("ARM: 9274/1: Add hwcap for Speculative Store Bypassing Safe") and hence
the corresponding changes added in 32-bit compat arm64 for similar user
interfaces.
Speculative Store Bypass Safe is a feature(FEAT_SSBS) present in
AArch32/AArch64 state for Armv8 and can be identified by PFR2.SSBS
identification register. This hwcap is already advertised in native arm64
kernel.
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230111053706.13994-8-amit.kachhap@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel/cpuinfo.c')
| -rw-r--r-- | arch/arm64/kernel/cpuinfo.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index d2b41f2544f5..876cd96c73ea 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -162,6 +162,7 @@ static const char *const compat_hwcap2_str[] = { [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", [COMPAT_KERNEL_HWCAP2(SB)] = "sb", + [COMPAT_KERNEL_HWCAP2(SSBS)] = "ssbs", }; #endif /* CONFIG_COMPAT */ |