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authorCatalin Marinas <catalin.marinas@arm.com>2022-05-20 20:50:57 +0300
committerCatalin Marinas <catalin.marinas@arm.com>2022-05-20 20:50:57 +0300
commite003d5335c3877bcbee8d0c347d3c3ee36cdd8b7 (patch)
treea73180a13d875674f1bc57ec0484b5d118d3e1ef /arch/arm64/kernel/fpsimd.c
parent201729d53a34924cfcd011f71e49de9bb2902bd8 (diff)
parentdffdeade18432d257e0c1845dc4e694f414a9721 (diff)
downloadlinux-e003d5335c3877bcbee8d0c347d3c3ee36cdd8b7.tar.xz
Merge branch 'for-next/sysreg-gen' into for-next/core
* for-next/sysreg-gen: (32 commits) : Automatic system register definition generation. arm64/sysreg: Generate definitions for FAR_ELx arm64/sysreg: Generate definitions for DACR32_EL2 arm64/sysreg: Generate definitions for CSSELR_EL1 arm64/sysreg: Generate definitions for CPACR_ELx arm64/sysreg: Generate definitions for CONTEXTIDR_ELx arm64/sysreg: Generate definitions for CLIDR_EL1 arm64/sve: Generate ZCR definitions arm64/sme: Generate defintions for SVCR arm64/sme: Generate SMPRI_EL1 definitions arm64/sme: Automatically generate SMPRIMAP_EL2 definitions arm64/sme: Automatically generate SMIDR_EL1 defines arm64/sme: Automatically generate defines for SMCR arm64/sysreg: Support generation of RAZ fields arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.h arm64/sme: Standardise bitfield names for SVCR arm64/sme: Drop SYS_ from SMIDR_EL1 defines arm64/fp: Rename SVE and SME LEN field name to _WIDTH arm64/fp: Make SVE and SME length register definition match architecture arm64/sysreg: fix odd line spacing arm64/sysreg: improve comment for regs without fields ...
Diffstat (limited to 'arch/arm64/kernel/fpsimd.c')
-rw-r--r--arch/arm64/kernel/fpsimd.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
index a6eee3fa3448..c5677aa2e9e6 100644
--- a/arch/arm64/kernel/fpsimd.c
+++ b/arch/arm64/kernel/fpsimd.c
@@ -393,7 +393,7 @@ static void task_fpsimd_load(void)
if (test_thread_flag(TIF_SME))
sme_set_vq(sve_vq_from_vl(sme_vl) - 1);
- write_sysreg_s(current->thread.svcr, SYS_SVCR_EL0);
+ write_sysreg_s(current->thread.svcr, SYS_SVCR);
if (thread_za_enabled(&current->thread))
za_load_state(current->thread.za_state);
@@ -445,15 +445,15 @@ static void fpsimd_save(void)
if (system_supports_sme()) {
u64 *svcr = last->svcr;
- *svcr = read_sysreg_s(SYS_SVCR_EL0);
+ *svcr = read_sysreg_s(SYS_SVCR);
- *svcr = read_sysreg_s(SYS_SVCR_EL0);
+ *svcr = read_sysreg_s(SYS_SVCR);
- if (*svcr & SYS_SVCR_EL0_ZA_MASK)
+ if (*svcr & SVCR_ZA_MASK)
za_save_state(last->za_state);
/* If we are in streaming mode override regular SVE. */
- if (*svcr & SYS_SVCR_EL0_SM_MASK) {
+ if (*svcr & SVCR_SM_MASK) {
save_sve_regs = true;
save_ffr = system_supports_fa64();
vl = last->sme_vl;
@@ -851,8 +851,8 @@ int vec_set_vector_length(struct task_struct *task, enum vec_type type,
sve_to_fpsimd(task);
if (system_supports_sme() && type == ARM64_VEC_SME) {
- task->thread.svcr &= ~(SYS_SVCR_EL0_SM_MASK |
- SYS_SVCR_EL0_ZA_MASK);
+ task->thread.svcr &= ~(SVCR_SM_MASK |
+ SVCR_ZA_MASK);
clear_thread_flag(TIF_SME);
}
@@ -1914,10 +1914,10 @@ void __efi_fpsimd_begin(void)
__this_cpu_write(efi_sve_state_used, true);
if (system_supports_sme()) {
- svcr = read_sysreg_s(SYS_SVCR_EL0);
+ svcr = read_sysreg_s(SYS_SVCR);
if (!system_supports_fa64())
- ffr = svcr & SYS_SVCR_EL0_SM_MASK;
+ ffr = svcr & SVCR_SM_MASK;
__this_cpu_write(efi_sm_state, ffr);
}
@@ -1927,8 +1927,8 @@ void __efi_fpsimd_begin(void)
ffr);
if (system_supports_sme())
- sysreg_clear_set_s(SYS_SVCR_EL0,
- SYS_SVCR_EL0_SM_MASK, 0);
+ sysreg_clear_set_s(SYS_SVCR,
+ SVCR_SM_MASK, 0);
} else {
fpsimd_save_state(this_cpu_ptr(&efi_fpsimd_state));
@@ -1961,9 +1961,9 @@ void __efi_fpsimd_end(void)
*/
if (system_supports_sme()) {
if (__this_cpu_read(efi_sm_state)) {
- sysreg_clear_set_s(SYS_SVCR_EL0,
+ sysreg_clear_set_s(SYS_SVCR,
0,
- SYS_SVCR_EL0_SM_MASK);
+ SVCR_SM_MASK);
if (!system_supports_fa64())
ffr = efi_sm_state;
}