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| author | Ard Biesheuvel <ardb@kernel.org> | 2023-01-11 13:22:35 +0300 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2023-01-24 14:51:08 +0300 |
| commit | 3dcf60bbfd284e5ebfa40c56172222425d10abf0 (patch) | |
| tree | 6af09231e1e0d8eed859f0d030fef188710a17c5 /arch/arm64/kernel/sleep.S | |
| parent | 32b135a7fafebe7843abe5425159fa081ae56b7c (diff) | |
| download | linux-3dcf60bbfd284e5ebfa40c56172222425d10abf0.tar.xz | |
arm64: head: Clean the ID map and the HYP text to the PoC if needed
If we enter with the MMU and caches enabled, the bootloader may not have
performed any cache maintenance to the PoC. So clean the ID mapped page
to the PoC, to ensure that instruction and data accesses with the MMU
off see the correct data. For similar reasons, clean all the HYP text to
the PoC as well when entering at EL2 with the MMU and caches enabled.
Note that this means primary_entry() itself needs to be moved into the
ID map as well, as we will return from init_kernel_el() with the MMU and
caches off.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20230111102236.1430401-6-ardb@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/kernel/sleep.S')
| -rw-r--r-- | arch/arm64/kernel/sleep.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S index 7b7c56e04834..2ae7cff1953a 100644 --- a/arch/arm64/kernel/sleep.S +++ b/arch/arm64/kernel/sleep.S @@ -99,6 +99,7 @@ SYM_FUNC_END(__cpu_suspend_enter) .pushsection ".idmap.text", "awx" SYM_CODE_START(cpu_resume) + mov x0, xzr bl init_kernel_el mov x19, x0 // preserve boot mode #if VA_BITS > 48 |